editor's blog
Subscribe Now

Next-Generation Image Signal Processor

Imagination Technologies has announced a new image signal processing architecture that they’re calling “Raptor.” The overarching concept is that the image signal processor (ISP) should no longer be a separate chip: it should be integrated into the main system SoC, along with the other related accelerators, CPU, and GPU. Raptor is IP that allows such integration. It’s targeted at next-generation image processing applications like feature identification, scalable for both low- and high-end applications.

The benefits they tout come both from this integration and the fact that they provide all of the pieces required between the raw camera sensor(s) and final RGB or YUV output or an encoded image or stream. Within the ISP itself, they are able to leverage the fact that all of the technology comes from the same place – with similar compression and a unified architecture. They say that this keeps latency low and supports their “Zero-memory” approach to delivering the image to encoders and various effects accelerators.

Of course, having all of this on the SoC reduces the chip-to-chip overhead of an external ISP. The ISP also gets the process advantages of the advanced nodes typically used for an SoC.

The architecture is intended to support multiple sensors, maintaining up to four concurrent contexts. These could be front- and back-side cameras on a phone, for example, or they could be multiple cameras for multi-camera arrays, stereoscopic imaging, or “integral photography,” where multiple images are stitched together to form what can be an almost 3D image with holographic tendencies. They support up to 16-bit pixel depth, scalable to the needs of the application.

Raptor_block-diagram_red.jpg

Custom processing can also be implemented by tagging the image data at various points in the pipeline and then running that data back into the pipeline. The image statistics are gathered as the image is processed; those statistics are available to the encoders, eliminating one encoding pass.

Availability is targeted for the first quarter of 2014. You can find more information in their announcement.

9 thoughts on “Next-Generation Image Signal Processor”

  1. Pingback: puffco plus or
  2. Pingback: binaural
  3. Pingback: DMPK
  4. Pingback: juegos friv
  5. Pingback: jeux de friv
  6. Pingback: bandar bola
  7. Pingback: Aws Alkhazraji

Leave a Reply

featured blogs
Jan 24, 2020
Someone has created a song by taking Pi, assigning each number to a note, and adding harmonies. The result is strangely captivating....
Jan 24, 2020
[From the last episode: We looked at the different ways memory can be organized in different kinds of systems.] Let'€™s look at a scenario: you run a restaurant, but you'€™re short on funds to hire people. So you'€™re your own chief cook and bottle-washer. You do everyt...
Jan 23, 2020
Embedded design trends typically revolve around three main ideas: faster data rates, smaller form factors and cost-effective solutions. Those design trends drive the theme for the 2020 Embedded Tech Trends forum: The Business and Technology Forum for Critical and Intelligent ...
Jan 22, 2020
Master the design and verification of next gen transport: Part One – Overview Master the design and verification of next gen transport: Part Two – High-Level Synthesis Master the design and verification of next gen transport: Part Three – Functional Safety M...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Drive Your Next Design to Completion Today with DesignWare IP® for Automotive SoCs