editor's blog
Subscribe Now

SPICE-ing It Up

SPICE is pretty fundamental to circuit design. That’s obvious for cell and custom designers; for you digital folks, you get exempted only because a cell designer already did the work for you. And, as with everything EDA, things are getting harder to compute with each process node.

Part of it is incremental. New nodes come with increasingly important parasitic modeling. That’s always been the case from generation to generation, not because of new parasitics, but because of old ones that used to be ignored that now mattered. But with FinFETs, you have those plus complex new parasitic relationships that have never been there before.

Cadence says that, despite the fact that the “H” in HSIM* stands for “hierarchical,” this hierarchy gets screwed up by the Rs and Cs. Lose the hierarchy and you lose the performance advantage it provides.

There’s another change that’s made life tougher for SPICE. In earlier days, performance could be increased by partitioning the job into channels, with PMOS transistors connected to VDD and NMOS to ground. But power gating has screwed that all up: those connections aren’t direct anymore because of the gates in the way. The power network had to be solved separately from the design, with the result munged back together at the end.

And so performance has suffered. Cadence’s latest SPICE XPS (eXtensive Partitioning Simulator) algorithms are said to use new partitioning algorithms that scale more linearly than their earlier exponential versions. Performance with power gating has returned to what it was in the old days before power gating. They’re touting a 10X improvement in speed, along with fewer required computing resources.

And how, you might ask, are they doing the partitioning now? I did ask. And they’re not saying.

Their current release is optimized for memory. Mixed signal designs will run, but not quite as fast; they’re anticipating that being optimized in the first half of 2014.

You can read more in their announcement.

 

*Edited to fix the error noted below…

Leave a Reply

featured blogs
Apr 9, 2021
You probably already know what ISO 26262 is. If you don't, then you can find out in several previous posts: "The Safest Train Is One that Never Leaves the Station" History of ISO 26262... [[ Click on the title to access the full blog on the Cadence Community s...
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...
Apr 7, 2021
We explore how EDA tools enable hyper-convergent IC designs, supporting the PPA and yield targets required by advanced 3DICs and SoCs used in AI and HPC. The post Why Hyper-Convergent Chip Designs Call for a New Approach to Circuit Simulation appeared first on From Silicon T...
Apr 5, 2021
Back in November 2019, just a few short months before we all began an enforced… The post Collaboration and innovation thrive on diversity appeared first on Design with Calibre....

featured video

Learn the basics of Hall Effect sensors

Sponsored by Texas Instruments

This video introduces Hall Effect, permanent magnets and various magnetic properties. It'll walk through the benefits of Hall Effect sensors, how Hall ICs compare to discrete Hall elements and the different types of Hall Effect sensors.

Click here for more information

featured paper

Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500

Sponsored by Texas Instruments

Functional safety standards such as IEC 61508 and ISO 26262 require semiconductor device manufacturers to address both systematic and random hardware failures. Base failure rates (BFR) quantify the intrinsic reliability of the semiconductor component while operating under normal environmental conditions. Download our white paper which focuses on two widely accepted techniques to estimate the BFR for semiconductor components; estimates per IEC Technical Report 62380 and SN 29500 respectively.

Click here to download the whitepaper

Featured Chalk Talk

Single Pair Ethernet

Sponsored by Mouser Electronics and HARTING

Industry 4.0 brings serious demands on communication connections. Designers need to consider interoperability, processing, analytics, EMI reduction, field rates, communication protocols and much more. In this episode of Chalk Talk, Amelia Dalton chats with Piotr Polak and McKenzie Reed of Harting about using single-pair Ethernet for Industry 4.0.

Click here for more information about HARTING T1 Industrial Single Pair Ethernet (SPE) Products