editor's blog
Subscribe Now

SPICE-ing It Up

SPICE is pretty fundamental to circuit design. That’s obvious for cell and custom designers; for you digital folks, you get exempted only because a cell designer already did the work for you. And, as with everything EDA, things are getting harder to compute with each process node.

Part of it is incremental. New nodes come with increasingly important parasitic modeling. That’s always been the case from generation to generation, not because of new parasitics, but because of old ones that used to be ignored that now mattered. But with FinFETs, you have those plus complex new parasitic relationships that have never been there before.

Cadence says that, despite the fact that the “H” in HSIM* stands for “hierarchical,” this hierarchy gets screwed up by the Rs and Cs. Lose the hierarchy and you lose the performance advantage it provides.

There’s another change that’s made life tougher for SPICE. In earlier days, performance could be increased by partitioning the job into channels, with PMOS transistors connected to VDD and NMOS to ground. But power gating has screwed that all up: those connections aren’t direct anymore because of the gates in the way. The power network had to be solved separately from the design, with the result munged back together at the end.

And so performance has suffered. Cadence’s latest SPICE XPS (eXtensive Partitioning Simulator) algorithms are said to use new partitioning algorithms that scale more linearly than their earlier exponential versions. Performance with power gating has returned to what it was in the old days before power gating. They’re touting a 10X improvement in speed, along with fewer required computing resources.

And how, you might ask, are they doing the partitioning now? I did ask. And they’re not saying.

Their current release is optimized for memory. Mixed signal designs will run, but not quite as fast; they’re anticipating that being optimized in the first half of 2014.

You can read more in their announcement.

 

*Edited to fix the error noted below…

Leave a Reply

featured blogs
Apr 22, 2019
Last week, Cadence announced the certification of its LPDDR4 IP in TSMC's 16nm automotive process. The opening paragraph of the press release actually says: Cadence Design Systems, Inc today... [[ Click on the title to access the full blog on the Cadence Community site....
Apr 19, 2019
As platforms become more electrical, and the safety of flying becomes paramount, the FAA'€™s EWIS regulations serve as a cornerstone to modern aircraft wiring compliance and safety certification. EWIS (rhymes with '€œGee whiz'€) is both a concept and practice that embr...
Apr 18, 2019
Thermal Shock testing isn’t unique to the connector world, but it does play a big role in the qualification testing that Samtec puts all connectors through before they are released for production. Chances are likely that you thermally shock many items per day and don...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...