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Palladium Hybrid

Cadence has announced its latest upgrade to their Palladium emulator family. It has many of the usual improvements you might expect – faster execution, higher capacity, better debug, and such. But there are two other new features that are more than incremental.

The first hybridizes verification between a virtual platform and the emulator. This is not the same as, say, simulation acceleration, where a simulator is running a cycle-accurate model and using the emulator to speed up the particularly intensive bits. In that model, the emulator is “slave” to the simulator.

In the hybrid model they’ve announced, it’s almost the inverse of that: the emulator is doing the real verification; a virtual platform is employed to speed up non-critical elements.

An obvious example of that is OS bring-up. If you’re actually testing the OS loading process to see if it works and to find bugs, then doing that on the emulator is necessary to model the true hardware cycle by cycle.

But once you have that done, then re-running the OS load each time you want to test something after that is not a good use of time. So the virtual platform can do that and then establish the state from which the emulator can continue. It’s more versatile than simple save-and-restore because you can instruct the virtual platform to do things differently each time if you want.

In this model, the overall SoC (or whatever) and its state are distributed between the virtual platform and the emulator. But it’s key to remember that the virtual platform is running abstracted models while the emulator is running the actual circuits. So anything that’s truly being verified needs to be in the emulator: the stuff in the virtual platform is assumed to be correct (at least for the purposes of the test being run – you could always swap it later).

Typically, the processor would be in the virtual platform and things like graphics and other accelerators would be in the emulator. (Unless you’re actually testing out the processor…)

Cadence says that the tricky part was achieving synchronization between the virtual platform and the emulator to make sure that they can each do their own thing when that makes sense – but that they check in and synchronize with each other where needed. This is essential for ensuring that, at any given time, the combined emulator/virtual platform entity is in a valid state.

Using this model, parts of the execution that don’t matter except to establish a correct state for some other test can be hurried along, slowing down only when the block-under-test is being exercised. The result they claim is 10X faster hardware/software verification and 60X faster OS bring-up.

The other new element is the ability to download virtual testbench elements like data generators into the Palladium for software-based execution. This may sound a bit like the VirtuaLAB thing we discussed last year, but there’s a critical difference. While they’re both intended to get rid of the rate matchers necessary to interface real data sources to the emulator, the VirtuaLAB approach is via pizza-box hardware as an accessory to the emulator. Cadence’s approach involves no new hardware because it’s simply software executed in the existing Palladium hardware.

You can get more details in their release.

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