One of the defining characteristics of an embedded system is that you should have no expectations about what it’s made of or how it’s arranged. There are no architecture standards, and that’s how everyone likes it.

Well, ok; not everyone: the poor dudes writing tools for embedded systems have a heck of a challenge dealing with all the variety. And, frankly, some of those tools come full circle and help architects decide how to optimize their systems. But if each variant takes a major project to configure the tools, then that’s not going to work.

Of course, we could try and standardize hardware architectures…

Yeah, good luck getting that one to go anywhere.

Instead, there’s a middle ground being explored by the Multicore Association: it’s called SHIM, which stands for Software-Hardware Interface for Multi-many-core. The idea is to give software tools a way to discover the hardware configuration via an XML file.

This is one of those projects where “restraint” is the name of the game. It would be really easy for something like this to get out of control and far exceed its scope, but the folks driving this – in particular Masaki Gondo of eSOL – are taking great pains to define what this is and isn’t.

For instance, it’s not a complete hardware description of everything in the system. It’s restricted to documenting hardware that matters to software, and it describes the hardware in a manner that makes sense to software (unlike IP-XACT, which is intended for hardware designers). Things like defining the type and number of processor cores, synchronization mechanisms, inter-core communications, memory architecture, interconnect, and virtualization scheme.

They also take pains to ensure that this is not a functional hardware model – you’re not going to plug it into some simulator and have it work. It’s just a description. It’s also not a tool in and of itself; it’s a format for data that can be consumed by tools that others create. So there’s really no threat to anyone in the ecosystem.

It’s partly intended to allow performance estimation of a given architecture, but it won’t be 100% cycle-accurate. It will help with the creation of – but will not auto-create – hardware abstraction layers.

The specific news here is that a working group is starting up to define the details; the first spec should be out sometime next year. You can find more info on the effort and how to participate in their release.