editor's blog
Subscribe Now

A Software View of Hardware

One of the defining characteristics of an embedded system is that you should have no expectations about what it’s made of or how it’s arranged. There are no architecture standards, and that’s how everyone likes it.

Well, ok; not everyone: the poor dudes writing tools for embedded systems have a heck of a challenge dealing with all the variety. And, frankly, some of those tools come full circle and help architects decide how to optimize their systems. But if each variant takes a major project to configure the tools, then that’s not going to work.

Of course, we could try and standardize hardware architectures…

Yeah, good luck getting that one to go anywhere.

Instead, there’s a middle ground being explored by the Multicore Association: it’s called SHIM, which stands for Software-Hardware Interface for Multi-many-core. The idea is to give software tools a way to discover the hardware configuration via an XML file.

This is one of those projects where “restraint” is the name of the game. It would be really easy for something like this to get out of control and far exceed its scope, but the folks driving this – in particular Masaki Gondo of eSOL – are taking great pains to define what this is and isn’t.

For instance, it’s not a complete hardware description of everything in the system. It’s restricted to documenting hardware that matters to software, and it describes the hardware in a manner that makes sense to software (unlike IP-XACT, which is intended for hardware designers). Things like defining the type and number of processor cores, synchronization mechanisms, inter-core communications, memory architecture, interconnect, and virtualization scheme.

They also take pains to ensure that this is not a functional hardware model – you’re not going to plug it into some simulator and have it work. It’s just a description. It’s also not a tool in and of itself; it’s a format for data that can be consumed by tools that others create. So there’s really no threat to anyone in the ecosystem.

It’s partly intended to allow performance estimation of a given architecture, but it won’t be 100% cycle-accurate. It will help with the creation of – but will not auto-create – hardware abstraction layers.

The specific news here is that a working group is starting up to define the details; the first spec should be out sometime next year. You can find more info on the effort and how to participate in their release.

Leave a Reply

featured blogs
Sep 21, 2021
Placing component leads accurately as per the datasheet is an important task while creating a package footprint symbol. As the pin pitch goes down, the size and location of the component lead play a... [[ Click on the title to access the full blog on the Cadence Community si...
Sep 21, 2021
Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging. The post High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1 appeared first on From Silicon To Softw...
Sep 18, 2021
Projects with a steampunk look-and-feel incorporate retro-futuristic technology and aesthetics inspired by 19th-century industrial steam-powered machinery....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Enter the InnovateFPGA Design Contest to Solve Real-World Sustainability Problems

Sponsored by Intel

The Global Environment Facility (GEF) Small Grants Programme, implemented by the U.N. Development Program, is collaborating with the #InnovateFPGA contest to support 7 funded projects that are looking for technical solutions in biodiversity, sustainable agriculture, and marine conservation. Contestants have access to the Intel® Cyclone® V SoC FPGA in the Cloud Connectivity Kit, Analog Devices plug-in boards, and Microsoft Azure IoT.

Learn more about the contest and enter here by September 30, 2021

featured paper

Configure the charge and discharge current separately in a reversible buck/boost regulator

Sponsored by Maxim Integrated (now part of Analog Devices)

The design of a front-end converter can be made less complicated when minimal extra current overhead is required for charging the supercapacitor. This application note explains how to configure the reversible buck/boost converter to achieve a lighter impact on the system during the charging phase. Setting the charge current requirement to the minimum amount keeps the discharge current availability intact.

Click to read more

featured chalk talk

Microwave/Millimeter Cable Assemblies and Interconnects

Sponsored by Mouser Electronics and Samtec

Cabling and connectors for RF design are critical to performance. And, in the world of microwave and millimeter-wave design, choosing the right interconnect for your frequency band is key to signal integrity. In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns of Samtec about what you need to know to choose the right interconnect solution for your next RF design.

Click here for more information about Samtec Precision RF Connectors & Cable Assemblies