editor's blog
Subscribe Now

Extreme Compilers for Extreme Architectures

ACE calls them “extreme architectures.” These are the processors that your mother told you to avoid because they’re just too darn hard to support. You can come up with the niftiest hardware features, but who’s going to figure out how to turn C code into something that will take advantage of them?

Well, ACE would say, “Don’t listen to your mother.” Their CoSy tool (I keep wanting to pronounce this “Co-Sigh,” you know, kind of like when you both lay back and realize that you both have something you need to talk about… but actually, ACE pronounces it “cozy”…) can take bizarre architectures and help you generate a compiler than optimizes the code it generates from a C program.

Where do you find these processors? In those dark alleys your mother told you to avoid? Perhaps… There might be one in that headset that that shady character is wearing. Don’t ask to take it apart and check; take our word for it.

But deeply-embedded processors that look nothing like the kind your mother likes, resembling them only in that they run code; they are found in the dark recesses of systems where every cycle counts for very specific functions. Like audio. Or video or communications or… well, your imagination is the limit.

Down there, you can sneer at power-of-two bit widths. You want precisely 11 bits? 17 bits? 19 bits? (These are prime examples…) You can do it, and CoSy will help you produce a compiler that allows a C program to use that data. You can also set custom alignment.

And the supported architectures don’t have to be on some “Here are the supported bizarre architectures”  list. If you build your own via ARC (now Synopsys) or Tensilica (now Cadence), for example, you can still use CoSy to generate the compiler.

You can find out more about their latest edition in their announcement.

Leave a Reply

featured blogs
May 24, 2024
Could these creepy crawly robo-critters be the first step on a slippery road to a robot uprising coupled with an insect uprising?...
May 23, 2024
We're investing in semiconductor workforce development programs in Latin America, including government and academic partnerships to foster engineering talent.The post Building the Semiconductor Workforce in Latin America appeared first on Chip Design....

featured paper

Achieve Greater Design Flexibility and Reduce Costs with Chiplets

Sponsored by Keysight

Chiplets are a new way to build a system-on-chips (SoCs) to improve yields and reduce costs. It partitions the chip into discrete elements and connects them with a standardized interface, enabling designers to meet performance, efficiency, power, size, and cost challenges in the 5 / 6G, artificial intelligence (AI), and virtual reality (VR) era. This white paper will discuss the shift to chiplet adoption and Keysight EDA's implementation of the communication standard (UCIe) into the Keysight Advanced Design System (ADS).

Dive into the technical details – download now.

featured chalk talk

VITA RF Product Portfolio: Enabling An OpenVPX World
Sponsored by Mouser Electronics and Amphenol
Interoperability is a very valuable aspect of military and aerospace electronic designs and is a cornerstone to VITA, OpenVPX and SOSA. In this episode of Chalk Talk, Amelia Dalton and Eddie Alexander from Amphenol SV explore Amphenol SV’s portfolio of VITA RF solutions. They also examine the role that SOSA plays in the development of military and aerospace systems and how you can utilize Amphenol SV’s VITA RF solutions in your next design.
Oct 25, 2023
27,273 views