editor's blog
Subscribe Now

Extreme Compilers for Extreme Architectures

ACE calls them “extreme architectures.” These are the processors that your mother told you to avoid because they’re just too darn hard to support. You can come up with the niftiest hardware features, but who’s going to figure out how to turn C code into something that will take advantage of them?

Well, ACE would say, “Don’t listen to your mother.” Their CoSy tool (I keep wanting to pronounce this “Co-Sigh,” you know, kind of like when you both lay back and realize that you both have something you need to talk about… but actually, ACE pronounces it “cozy”…) can take bizarre architectures and help you generate a compiler than optimizes the code it generates from a C program.

Where do you find these processors? In those dark alleys your mother told you to avoid? Perhaps… There might be one in that headset that that shady character is wearing. Don’t ask to take it apart and check; take our word for it.

But deeply-embedded processors that look nothing like the kind your mother likes, resembling them only in that they run code; they are found in the dark recesses of systems where every cycle counts for very specific functions. Like audio. Or video or communications or… well, your imagination is the limit.

Down there, you can sneer at power-of-two bit widths. You want precisely 11 bits? 17 bits? 19 bits? (These are prime examples…) You can do it, and CoSy will help you produce a compiler that allows a C program to use that data. You can also set custom alignment.

And the supported architectures don’t have to be on some “Here are the supported bizarre architectures”  list. If you build your own via ARC (now Synopsys) or Tensilica (now Cadence), for example, you can still use CoSy to generate the compiler.

You can find out more about their latest edition in their announcement.

Leave a Reply

featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....

featured video

How NV5, NVIDIA, and Cadence Collaboration Optimizes Data Center Efficiency, Performance, and Reliability

Sponsored by Cadence Design Systems

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Click here for more information about Cadence Data Center Solutions

featured chalk talk

The Future of Intelligent Devices is Here
Sponsored by Alif Semiconductor
In this episode of Chalk Talk, Amelia Dalton and Henrik Flodell from Alif Semiconductor explore the what, where, and how of Alif’s Ensemble 32-bit microcontrollers and fusion processors. They examine the autonomous intelligent power management, high on-chip integration and isolated security subsystem aspects of these 32-bit microcontrollers and fusion processors, the role that scalability plays in this processor family, and how you can utilize them for your next embedded design.
Aug 9, 2023
40,278 views