editor's blog
Subscribe Now

SystemC HLS Optimizes Power

Forte occupies what you might call a middle level in logic synthesis. We’ve talked about the positioning before, but a concise way of looking at it might be as follows:

  • ANSI C/C++ provides an unstructured, untimed description of the design.
  • SystemC provides a structured, untimed description of the design.
  • RTL provides a structured, timed description of the design.

The middle one isn’t quite that simple: the interfaces are timed, either at the transaction or pin level. But the timing of what goes on inside is a product of synthesis and is subject to tradeoffs.

In an update conversation at DAC, Forte noted that one of the big improvements to their latest high-level synthesis (HLS) release, Cynthesizer 5, is the ability to include power in the tradeoffs in addition to performance and area. This actually required a complete redo of the underlying infrastructure, so much of the code is brand new.

One of the outcomes of that rework was to change how scheduling and allocation are done. For a given microarchitecture, scheduling refers to the process of assigning an event to a particular clock edge. For example, if two streams of logic converge and one needs eight clock cycles to complete and the other only three, then you could have the short-chain logic start early and then wait (“eager”) or start just-in-time to arrive with the long logic chain (“lazy”). Allocation assigns resources.

Their tools used to do scheduling first and then allocation. Now they happen at the same time, which means they can be co-optimized.

They can also do more design space exploration, with Monte Carlo capabilities. An example of this would be in the selection of a multiplier. In the past, they had one multiplier architecture; now they have several, with different performance/power/area tradeoffs. After manually dialing in the number of choices to get close, you can use Monte Carlo analysis to figure out which is best. (The manual part is just to keep the design space from being too enormous.) A half hour or so typically allows the tool to sort through thousands of different configurations to find the optimal one(s).

Optimizing for power brings one new consideration into play: state machine encoding. You generally want to minimize the number of bits switching (and even gate clocks to hit only the register that’s going to change). But one-hot, which is the extreme example, requires too many flip-flops. So they have a statistical algorithm that determines, short of one-hot, what the lowest-power encoding scheme would be.

Finally, they’ve put an algorithm viewer into the tool to allow the guys doing the implementation, who likely received it from the guy who wrote the algorithm, to get a better feel for what’s going on in the algorithm itself.

You can find more about their latest update in their announcement.

Leave a Reply

featured blogs
Feb 27, 2021
New Edge Rate High Speed Connector Set Is Micro, Rugged Years ago, while hiking the Colorado River Trail in Rocky Mountain National Park with my two sons, the older one found a really nice Swiss Army Knife. By “really nice” I mean it was one of those big knives wi...
Feb 26, 2021
OMG! Three 32-bit processor cores each running at 300 MHz, each with its own floating-point unit (FPU), and each with more memory than you than throw a stick at!...
Feb 26, 2021
In the SPECTRE 20.1 base release, we released Spectre® XDP-HB as part of the new Spectre X-RF simulation technology. Spectre XDP-HB uses a highly distributed multi-machine multi-core simulation... [[ Click on the title to access the full blog on the Cadence Community si...

featured video

Silicon-Proven Automotive-Grade DesignWare IP

Sponsored by Synopsys

Get the latest on Synopsys' automotive IP portfolio supporting ISO 26262 functional safety, reliability, and quality management standards, with an available architecture for SoC development and safety management.

Click here for more information

featured paper

The Basics of Using the DS28S60

Sponsored by Maxim Integrated

This app note details how to use the DS28S60 cryptographic processor with the ChipDNA™. It describes the required set up of the DS28S60 and a step-by-step approach to use the asymmetric key exchange to securely generate a shared symmetric key between a host and a client. Next, it provides a walk through on how to use the symmetric key to exchange encrypted data between a Host and a Client. Finally, it gives an example of a bidirectional authentication process with the DS28S60 using an ECDSA.

Click here to download the whitepaper

Featured Chalk Talk

Electrification of the Vehicle

Sponsored by Mouser Electronics and KEMET

The automotive technology revolution has arrived, and with it - new demands on components for automotive applications. Electric vehicles, ADAS, connected cars, and autonomous driving put fresh demands on our electrical and electronic parts. In this episode of Chalk Talk, Amelia Dalton chats with Nick Stephen of KEMET about components for the next generation of automobiles.

More information about KEMET Electronics ALA7D & ALA8D Snap-In Capacitors