With the multi-domain power beasts being designed into today’s SoCs, it’s easy to miss a detail. Which is why verification is so much more important than it used to be, when inspection and a spreadsheet or two might have gotten you through.
So today you can get verification tools to help you to ensure that the voltages are right and that level shifters and isolation are all in place. But, in a recent announcement, Jasper claims to take things one step further: In addition to verifying the static structure of the power edifice, they can also verify the power sequencing.
They take in the design RTL and the power intent (either UPF for CPF) and, from that, create a model that can be verified using their formal technology. They say that they can check the power optimization structures, power management, and the sequencing. In conjunction with their other tools, they can also check to make sure that the power optimization circuits won’t screw something else in the design up.
You can read more in their release.