editor's blog
Subscribe Now

MEMS Measurement Standards

Consistent with a move towards standards in MEMS, NIST has released two reference chips that fabs can use to cross-check their measurement techniques. There are several critical parameters unique to MEMS, and five of them are captured by this 5-in-1 reference. NIST has done its own measurements, and the idea is to replicate the results they got. The chips are available for sale ($1735), along with the results for comparison.

The five tests covered are:

  • Young’s modulus
  • Residual strain
  • Strain gradient
  • Step height
  • In-plane length

There are two versions of the chip: one (RM 8096) uses a CMOS process with bulk micromachining, meaning that the structures are etched out of the bulk silicon. The other (RM 8097) uses surface micromachining to build the structures out of poly.

Each chip has additional test structures for things like tensile strength and line widths.

You can find more information on their summary page, and much more detail in their PDF proposals (bulk micro-machined here; surface micro-machined here).

Leave a Reply

featured blogs
Feb 24, 2021
mmWave applications are all the rage. Why? Simply put, the 5G tidal wave is coming. Also, ADAS systems use 24 GHz for SRR applications and 77 GHz for LRR applications. Obviously, the world needs mmWave tech! Traditional mmWave technology spans the frequency range of 30 –...
Feb 24, 2021
Crowbits are programmable, LEGO-compatible, magnetically-coupled electronic blocks to interest kids in electronics and computing and facilitate their STEM activities....
Feb 24, 2021
With DVCon 2021 on the horizon we share a primer on our datapath verification technology HECTOR, exploring its impact on machine learning & AI chip design. The post Why Datapath Validation Is Important'€”and How HECTOR Technology Can Help appeared first on From Silico...
Feb 24, 2021
When I worked for Cadence back in the early oughts, we developed a layout database called OpenAccess, usually abbreviated to OA. It had actually been designed from the ground up to be the native... [[ Click on the title to access the full blog on the Cadence Community site. ...

featured video

Silicon-Proven Automotive-Grade DesignWare IP

Sponsored by Synopsys

Get the latest on Synopsys' automotive IP portfolio supporting ISO 26262 functional safety, reliability, and quality management standards, with an available architecture for SoC development and safety management.

Click here for more information

featured paper

Ultra Portable IO On The Go

Sponsored by Maxim Integrated

The Go-IO programmable logic controller (PLC) reference design (MAXREFDES212) consists of multiple software configurable IOs in a compact form factor (less than 1 cubic inch) to address the needs of industrial automation, building automation, and industrial robotics. Go-IO provides design engineers with the means to rapidly create and prototype new industrial control systems before they are sourced and constructed.

Click here to download the whitepaper

Featured Chalk Talk

Mom, I Have a Digital Twin? Now You Tell Me?

Sponsored by Cadence Design Systems

Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.

Click here for more information