editor's blog
Subscribe Now

Big and Little Core Combos

A long while back ARM introduced their big.LITTLE concept. (So cute how they put the big in little letters and the little in big letters! Did you notice that?) The general concept is to have one beefy processor for heavy lifting and one small one for light duty; by powering them up and down, you can save energy by assigning the right core to the right task.

But at last week’s Multicore DevCon, processor guru Linley Gwennap showed, among other things, various ways in which companies are implementing this concept. Although, of course, ARM figures in all of them.

  • Nvidia includes an A15 CompanionCore (their original whitepaper shows an A9). Yeah, an A15 is the “little.” The point is that, unlike the other A15s on the chip, this one is optimized on the low-power end of the process, so it has less performance but consumes less power.
  • Samsung is going more the way ARM suggested: pairing an A15 with an A7. The A7 is 3.3 times more power efficient in MIPS/W; twice as efficient in MIPS/m2. But the A15 is 3 times faster.
  • Samsung’s Octa is more complicated. It has 4 A15s and 4 A7s, all software compatible so that any software can run on any of them. Problem is, Android is running on it, and, for now, Android doesn’t like mixtures of core types: it want’s homogeneous (apparently a future rev won’t). So you can’t run both sets of four cores at the same time. If you want performance, then you run the four A15s and the A7s are powered off; if you want to run with lower power, then you shut the A15s down and power up the A7s and run them. That’s where the software compatibility is critical.
  • Qualcomm fakes it, you might say. They have an A15, and they just clock it way down to save power. This is almost as effective as using an A7.

Clearly lots of ways to skin that cat…

Leave a Reply

featured blogs
Jun 13, 2024
I've just been introduced to the DuoFlex 4K Dual-Screen Display from HalmaPixel, and now I'm drooling with desire all over my keyboard....

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured chalk talk

FleClear: TDK’s Transparent Conductive Ag Film
Sponsored by Mouser Electronics and TDK
In this episode of Chalk Talk, Amelia Dalton and Chris Burket from TDK investigate the what, where, and how of TDK’s transparent conductive Ag film called FleClear. They examine the benefits that FleClear brings to the table when it comes to transparency, surface resistance and haze. They also chat about how FleClear compares to other similar solutions on the market today and how you can utilize FleClear in your next design.
Feb 7, 2024
18,163 views