editor's blog
Subscribe Now

Big and Little Core Combos

A long while back ARM introduced their big.LITTLE concept. (So cute how they put the big in little letters and the little in big letters! Did you notice that?) The general concept is to have one beefy processor for heavy lifting and one small one for light duty; by powering them up and down, you can save energy by assigning the right core to the right task.

But at last week’s Multicore DevCon, processor guru Linley Gwennap showed, among other things, various ways in which companies are implementing this concept. Although, of course, ARM figures in all of them.

  • Nvidia includes an A15 CompanionCore (their original whitepaper shows an A9). Yeah, an A15 is the “little.” The point is that, unlike the other A15s on the chip, this one is optimized on the low-power end of the process, so it has less performance but consumes less power.
  • Samsung is going more the way ARM suggested: pairing an A15 with an A7. The A7 is 3.3 times more power efficient in MIPS/W; twice as efficient in MIPS/m2. But the A15 is 3 times faster.
  • Samsung’s Octa is more complicated. It has 4 A15s and 4 A7s, all software compatible so that any software can run on any of them. Problem is, Android is running on it, and, for now, Android doesn’t like mixtures of core types: it want’s homogeneous (apparently a future rev won’t). So you can’t run both sets of four cores at the same time. If you want performance, then you run the four A15s and the A7s are powered off; if you want to run with lower power, then you shut the A15s down and power up the A7s and run them. That’s where the software compatibility is critical.
  • Qualcomm fakes it, you might say. They have an A15, and they just clock it way down to save power. This is almost as effective as using an A7.

Clearly lots of ways to skin that cat…

Leave a Reply

featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....

featured video

How NV5, NVIDIA, and Cadence Collaboration Optimizes Data Center Efficiency, Performance, and Reliability

Sponsored by Cadence Design Systems

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Click here for more information about Cadence Data Center Solutions

featured chalk talk

Connectivity Solutions for Smart Trailers
Smart trailers can now be equipped with a wide variety of interconnection systems including wire-to-wire, wire-to-board, and high-speed data solutions. In this episode of Chalk Talk, Amelia Dalton and Blaine Dudley from TE Connectivity explore the evolution of smart trailer technology, the different applications within a trailer where connectivity would be valuable, and how TE Connectivity is encouraging innovation in the world of smart trailer technology.
Oct 6, 2023
35,830 views