I’m getting a sense that we’re back into the small-company-friendly phase of the EDA company cycle. A number of newcomers (which means they’ve been around working quietly for several years and are now launching) are knocking on doors.

Invarian is one such company, and they’ve launched two analysis platforms: their “InVar Pioneer Power Platform”, with power, IR-drop/EM, and thermal analysis, and their “InVar 3D Frontier Platform” for thermal analysis of 3D ICs.

Their claim to fame is that they’re the only tool that can handle true full-chip sign-off analysis at 28 nm and below, with SPICE accuracy and fast run times (“fast” being a relative term). In particular, for digital designs, they do concurrent analysis of timing, thermal, EM/IR, and power. Yeah, they have a timing engine – and they say it’s really good, too. But trying to displace PrimeTime as the gold standard is a tough call; that’s not their goal. So the timing engine serves the other pieces.

The whole concurrent thing means that, instead of running one analysis to completion and then handing those results to the next engine for different analysis, they run the engines together. As they iterate towards convergence, they update a common database on each cycle, so each engine is using a slightly-more-converged value from the other engines on every new cycle. They say that this speeds overall convergence, taking analysis that used to require several days to run and managing it in a few hours instead, with no loss of accuracy.

Of course, having a new tool also means that you can build in parallelism from the get-go, leveraging multicore and multi-machine computing resources.

For analog sign-off, they can do co-simulation with the usual SPICE suspects. And for 3D analysis for packages with multiple dice, they boast models that are more accurate and realistic than the standard JEDEC models. And they claim greater ease of use, making rules (which are constantly evolving) more manageable in particular.

You can find more in their release.