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Continued FinFET Roll

The Synopsys Users’ Group scheduled a panel session on FinFETs at their recent session. This is consistent with pretty much every EDA company providing FinFET content for their users; they’re the latest hot topic, and represent a non-trivial change.

But the popularity of the topic was driven home rather starkly. They used the auditorium at the Santa Clara Convention Center, and even so, it was standing-room only, and many, many people had to be turned away when there wasn’t more room for standing. So interest was obviously quite keen. Which reflect the fact that FinFETs are in transition: once the far-out concept for some future technology node, this stuff is becoming real for lots of real engineers.

And, for the most part, the panel said the usual things you might expect about why FinFETs are necessary or good and what’s different about using them. The Synopsys speaker talked about the tools, of course, but it was still too early to see the results of the lead lots they had put through.

And it was refreshing to have Cavium on the panel as a user, with the candor to discuss what they felt was the biggest drawback about FinFETs: parasitic capacitances. As in, there are too many of them. So they were having trouble keeping dynamic power down. They requested EDA help both in optimizing dynamic power consumption and with EM analysis.

Not that they thought that FinFETs were a bad idea in general; they agreed with the litany of benefits that is typically trotted out. But their willingness to say, “They’re good but…” helped give a real-world feel to the kind of panel that can too often be simply an echo chamber for laudatory talking points.

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