editor's blog
Subscribe Now

Continued FinFET Roll

The Synopsys Users’ Group scheduled a panel session on FinFETs at their recent session. This is consistent with pretty much every EDA company providing FinFET content for their users; they’re the latest hot topic, and represent a non-trivial change.

But the popularity of the topic was driven home rather starkly. They used the auditorium at the Santa Clara Convention Center, and even so, it was standing-room only, and many, many people had to be turned away when there wasn’t more room for standing. So interest was obviously quite keen. Which reflect the fact that FinFETs are in transition: once the far-out concept for some future technology node, this stuff is becoming real for lots of real engineers.

And, for the most part, the panel said the usual things you might expect about why FinFETs are necessary or good and what’s different about using them. The Synopsys speaker talked about the tools, of course, but it was still too early to see the results of the lead lots they had put through.

And it was refreshing to have Cavium on the panel as a user, with the candor to discuss what they felt was the biggest drawback about FinFETs: parasitic capacitances. As in, there are too many of them. So they were having trouble keeping dynamic power down. They requested EDA help both in optimizing dynamic power consumption and with EM analysis.

Not that they thought that FinFETs were a bad idea in general; they agreed with the litany of benefits that is typically trotted out. But their willingness to say, “They’re good but…” helped give a real-world feel to the kind of panel that can too often be simply an echo chamber for laudatory talking points.

Leave a Reply

featured blogs
Jul 5, 2022
The 30th edition of SMM , the leading international maritime trade fair, is coming soon. The world of shipbuilders, naval architects, offshore experts and maritime suppliers will be gathering in... ...
Jul 5, 2022
By Editorial Team The post Q&A with Luca Amaru, Logic Synthesis Guru and DAC Under-40 Innovators Honoree appeared first on From Silicon To Software....
Jun 28, 2022
Watching this video caused me to wander off into the weeds looking at a weird and wonderful collection of wheeled implementations....

featured video

Demo: Achronix Speedster7t 2D NoC vs. Traditional FPGA Routing

Sponsored by Achronix

This demonstration compares an FPGA design utilizing Achronix Speedster7t 2D Network on Chip (NoC) for routing signals with the FPGA device, versus using traditional FPGA routing. The 2D NoC provides a 40% reduction in logic resources required with 40% less compile time needed versus using traditional FPGA routing. Speedster7t FPGAs are optimized for high-bandwidth workloads and eliminate the performance bottlenecks associated with traditional FPGAs.

Subscribe to Achronix's YouTube channel for the latest videos on how to accelerate your data using FPGAs and eFPGA IP

featured paper

Addressing high-voltage design challenges with reliable and affordable isolation tech

Sponsored by Texas Instruments

Check out TI’s new white paper for an overview of galvanic isolation techniques, as well as how to improve isolated designs in electric vehicles, grid infrastructure, factory automation and motor drives.

Click to read more

featured chalk talk

Tackling Automotive Software Cost and Complexity

Sponsored by Mouser Electronics and NXP Semiconductors

With the sheer amount of automotive software cost and complexity today, we need a way to maximize software reuse across our process platforms. In this episode of Chalk Talk, Amelia Dalton and Daniel Balser from NXP take a closer look at the software ecosystem for NXP’s S32K3 MCU. They investigate how real-time drivers, a comprehensive safety software platform, and high performance security system will help you tackle the cost and complexity of automotive software development.

Click here for more information about NXP Semiconductors S32K3 Automotive General Purpose MCUs