editor's blog
Subscribe Now

Room-Temp Covalent Wafer Bonding

MEMS elements are delicate. They sit there in their little cavities, expecting to operate in some sort of controlled environment – perhaps a particular gas or pressure (or lack of it). And if they’re collocated with CMOS circuitry, then they need to be protected from any further processing steps. In other words, they need to be sealed off from the rest of the world. And wafer bonding is a common way to do that: bring another wafer (perhaps with etched features) face-to-face with the working wafer and get them to bond.

Covalent molecular bonds are the strongest; if you bring two silicon wafers together, for example, the ideal is to have the silicon atoms at the surface of each wafer bond covalently with their counterparts on the other wafer so that the whole thing starts to look like a continuous crystal. That’s the ideal.

Doing this isn’t trivial, of course, since the surfaces are likely to have imperfections and contaminants. So surface preparation has been an important part of the wafer bonding process. It has also involved intermediaries like water that establish a preliminary bond; an anneal then precipitates the reactions that result in the appropriate covalent bonds and out-diffusion of any extraneous elements.

Initially, high temperatures were required for the annealing. But, of course, anything over 450 °C won’t sit well with any CMOS that might be in place, so various surface preparation techniques have been devised to get the anneal temps down below that threshold.

But even these temperatures can be an issue for bonding unlike materials, or for wafers that have unlike materials in the stack, where stresses can result from differing rates of thermal expansion during the anneal process.

EVG has recently announced a new way of preparing the surface so that covalent bonding occurs immediately, at room temperature. To be clear, they have announced that they have this new process; they haven’t announced what it is; they’re still being coy on that. This eliminates the annealing step completely, and therefore the thermal expansion issue as well.

Equipment using this new technique should ship sometime this year. You can find out more in their release.

Leave a Reply

featured blogs
Nov 30, 2022
By Joe Davis Sponsored by France's ElectroniqueS magazine, the Electrons d'Or Award program identifies the most innovative products of the… ...
Nov 29, 2022
Smart manufacturing '“ the use of nascent technology within the industrial Internet of things (IIoT) to address traditional manufacturing challenges '“ is leading a supply chain revolution, resulting in smart, connected, and intelligent environments, capable of self-operati...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Maximizing Power Savings During Chip Implementation with Dynamic Refresh of Vectors

Sponsored by Synopsys

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn more about Energy-Efficient SoC Solutions

featured paper

How SHP in plastic packaging addresses 3 key space application design challenges

Sponsored by Texas Instruments

TI’s SHP space-qualification level provides higher thermal efficiency, a smaller footprint and increased bandwidth compared to traditional ceramic packaging. The common package and pinout between the industrial- and space-grade versions enable you to get the newest technologies into your space hardware designs as soon as the commercial-grade device is sampling, because all prototyping work on the commercial product translates directly to a drop-in space-qualified SHP product.

Click to read more

featured chalk talk

Tame the SiC Beast - Unleash the Full Capacity of Silicon Carbide

Sponsored by Mouser Electronics and Microchip

Wide band gap materials such as silicon carbide are revolutionizing the power industry. At the same time, they can also introduce byproducts including overheating, short circuits and over voltage. The question remains: how can we use silicon carbide without those headache-inducing side effects? In this episode of Chalk Talk, Amelia Dalton chats with Rob Weber from Microchip about Microchip’s patented augmented switching technology can make those silicon carbide side effects a thing of the past while reducing our switching losses up to 50% and accelerating our time to market as well.

Click here for more information about the Microsemi / Microchip AgileSwitch® ASDAK+ Augmented Switching™ Dev Kit