editor's blog
Subscribe Now

Dry Etch Edges Wet

Two announcements have come out recently regarding dry etch systems. Now… dry etch is nothing new. Although it is newer than wet etch, which is still being used. And, as they say, therein lies the rub.

The first announcement came late January regarding a new system shipping from Memsstar. Their focus was on MEMS, and, in particular, on reducing yield failures due to stiction. There are two pieces to this move.

First, they note that wet etch processes must be followed by a wash to clean out all of the etchant and resulting groddy bits. This involves water, and it’s very easy for bits of water to get “caught” in small spaces due to capillary action. It’s generally not a good idea to have residues like that any place in the circuit, but if it happens to be touching a moving MEMS element, then it may cause the element to bind (or, at the very least, not move with the same force/acceleration relationships as were designed for). This is a form of stiction.

Dry etch processes do not involve a wash, and so simply moving away from wet etch might seem sufficient. But in particular with an HF dry etch, one of the products of the reaction is water. It’s normally in gaseous form, where it won’t cause stiction issues. But, according to Memsstar, if the reaction isn’t properly controlled, you can get excess water, some of which may then liquefy, in which case you’re back to dealing with stiction.

So part two of this move is their claim of having the only system with the process monitoring that can ensure this doesn’t happen. So you go from a two-step wet etch process (etch, wash) with stiction to a one-step dry etch process without stiction.

The other announcement was more recent; it was from Nanoplas. They actually got their start with a MEMS-oriented “high-density radical flux” (HDRF) etcher that, due to a source that provided a concentration of species 1000 times higher than a typical source, they could be much more efficient when cleaning out residues from irregular MEMS configurations, especially cavities and high-aspect-ratio features.

But their latest announcement is for what they call “atomic layer downstream etching,” or ALDE. And they can’t really say a lot about the details now due to patent filing issues. But their current focus for it is CMOS and the problems being encountered at 28, 20, and 14-nm nodes using traditional phosphoric acid wet etching.

Etching normally involves a measure of selectivity. You want to etch things you’re trying to remove without touching anything else. Unfortunately, nothing is perfect, so you always get some impact on the stuff you’re trying to keep; a measure of the selectivity is the ratio of how much you etch what you’re trying to remove vs. how much you etch what you’re trying to keep. Rates these days can be 10:1 or even 50:1.

But, according to Nanoplas, from a process control standpoint, etch rate and selectivity have been tightly bound together. You can be more selective if you etch slower, so it’s hard to optimize for quality and throughput. Their claim is again about control: they say that, with their new source, they can independently control selectivity and etch rate.

Typically, there’s one thing you’re trying to etch, and everything else is what shouldn’t be etched. Which means there may be more than one material that needs preserving. But even if it’s just one (and Nanoplas says that it’s typically one or two), it could be oxide or silicon or resist or nitride or poly or metal or… you get the picture.

But they say that the control they provide allows the etch to be optimized for any of them. Right now, they’re focusing on SiN etch for a specific client that’s dissatisfied with the performance of traditional wet-etch approaches for spacer technology. But, going forward, they’ll be able to optimize for any other etches as well. Oxide and poly will be their next areas of work.

They won’t actually be selling a complete system, but rather a process module that OEMs can integrate into their platforms.

At such time as I can get more info on how the Nanoplas system works, I’ll follow up with those details.

 

You can find out more about the Memsstar system in their release; likewise, there’s some more detail on the Nanoplas announcement in their release.

Leave a Reply

featured blogs
Mar 9, 2026
What happens to our digital history when the world's biggest archive of retro video games disappears?...

featured video

Cadence Chiplets Solutions | Helping you realize your chiplet ambitions

Sponsored by Cadence Design Systems

In this webinar, David Glasco, VP of Compute Solutions at Cadence, discusses how Cadence enables customers to transition from traditional monolithic SoC architectures to modular, scalable chiplet-based solutions, essential for meeting the growing demands of physical AI applications and high-performance computing.

Read eBook: Helping You Realize Your Chiplet Ambitions

featured chalk talk

The Han® Connector
Sponsored by Mouser Electronics and HARTING
In this episode of Chalk Talk, Emily Kenny from HARTING and Amelia Dalton investigate the details of the HARTING Han® connector family. They also explore the trends in connector solutions today, the variety of options within this connector family and how you can get started using a HARTING Han® connector for your next design!
Feb 18, 2026
21,791 views