Conventional wisdom should suggest the following points:
- Each new process node affects all layers
- Moving to FinFETs will be a big change for designers
Turns out, according to EDA folks (Mentor and Cadence, to be specific), neither of those is true.
The backend of 16/14 (hereinafter referred to as 14 because I’m lazy) – the upper metal layers and such – will be the same as 20 nm. In fact, in this view, the easiest way to describe the 14-nm node is as a 20-nm process with FinFETs instead of planar transistors. At least as implemented by the folks doing FinFETs (which is all the obvious big foundry guys).
If the second bullet point is true, then this means a lot of work for designers when moving from 20 to 14. But the move to FinFET should be moderately transparent – for digital designers. That’s because the transistor itself is abstracted under many layers of design tool. Obviously the EDA tools themselves needed a ton of work – parasitic extraction in particular has become much more complex due to the complicated shapes, resulting in a gnarly model.
But the digital designer is largely protected from all that (at the expense of the cell builders). In fact, the 28à20-nm transition may have been the hard one, since that’s where double-patterning and local interconnect were introduced. Those have had more impact on designers (and, of course, on the tools).
As usual, things aren’t quite as simple for the analog guys. But the biggest change they face in how they work is the quantization that FinFETs introduce: gate “width” amounts to a number of FinFETs, and you can’t have a fractional FinFET. (OK, maybe you can end up with some, but they would be considered a yield problem.)