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One + One > Two

The latest, greatest mobile standards appear to be beastly affairs. Added to the old ones, and the number of algorithms that a poor cellphone – even a smart one – has to manage becomes pretty daunting.

And features like MIMO – various permutations and combinations of multiple antennae on the sending and receiving sides – make for an array of possible algorithms that CEVA says can only be managed through a software approach. That is, you load the software you need for the algorithm required at the moment rather than hard-code every possible variant, which would simply take too much silicon.

CEVA attacks this market with their XC architecture, and they recently beefed it up by announcing a multicore version. “OK, big deal,” you might say. “I had one core, now I can have more than one. I could do that before by instantiating more than one.”

Yes and no. Going truly multicore means one more huge addition to the architecture, most of which operates in the background: cache coherency. So even if that was all they had done, that’s a lot of work in its own right.

But they appear to have gone beyond that, adding packet management and scheduling hardware, along with design tools that understands higher-level concepts like queues and buffers. And frankly, at least conceptually, this starts to look a lot like a Cavium OCTEON chip, only with DSPs instead of RISC CPUs.

But, of course, this is IP, not hard silicon (although they have emulation boards). So you can configure things any way you want – including homogeneous and heterogeneous architectures, the latter blending DSPs and CPUs if desired.

They’ve also added floating point support; they point to the MIMO algorithms as a particularly compelling reason to move beyond fixed-point.

So it’s a larger leap than just adding another core or two. You can see more of the speeds and feeds in their release.

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