editor's blog
Subscribe Now

Connecting CNTs to Metal

One of the things about CNTs acting as transistors is that the current flowing through them has to get into and out of the CNT from some other substance – typically metal. That junction, as it turns out, can have significant resistance. According to a paper done by a team from Georgia Tech and MIT (Songkil Kim et al), for a single-walled CNT (SWCNT) to connect to metal, there’s a quantum limit of around 65 kΩ.

Multi-walled CNTs (MWCNTs) can provide much lower-resistance connections, but how low depends on how you do it. Sputtering or evaporation only gets you to 3-4 kΩ best case, with no contamination. You can get as low as 700 Ω using TEM-AFM and nano-manipulation + joule heating, but this isn’t a viable commercial process.

The team used E-beam-induced deposition (EBID), which is essentially a localized CVD, where the gas is decomposed with great control using an electron beam. The overall process consists of first graphitizing amorphous carbon and then forming the connections.

Annealing amorphous carbon into graphite proved something of a challenge. They tried using a current to create joule heating, but it was tough to control: as the annealing progressed, the resistance went down, driving up the current and leading to runaway that could cause damage. So they went to an oven instead. They had to keep the temperature at 350 °C, the temperature at which graphitization starts, to keep the CNTs from oxidizing at higher temperatures.

In order to connect the multiple walls that were formed to metal, they directed the e-beam near the connection point. At first they aimed slightly short of the connection, using the backscatter to connect the inner walls – kind of like a basketball layup. Then they focused directly on the connection to finish it up.

This was followed up by an anneal.

The results were as follows:

  • Before making the contact, resistance was in the GΩ range.
  • If only the outer wall was connected, they got a 3.8-kΩ connection.
  • The EBID process alone brought the resistance from GΩ to 300 kΩ.
  • A 10-minute anneal at 350 °C brought the resistance down to 1.4 kΩ.
  • A further 20-25 minutes of annealing brought the resistance all the way down to 116 Ω.

Note that, to the best of my knowledge, this process was not used by the team that created the first CNT sub-systems recently reported at ISSCC.

You can find out more details in the published paper, but note that it’s behind a paywall.

Leave a Reply

featured blogs
May 6, 2026
Hollywood has struck gold with The Lord of the Rings and Dune'”so which sci-fi and fantasy books should filmmakers tackle next?...

featured paper

Want early design analysis without simulation?

Sponsored by Siemens Digital Industries Software

Traditional verification methods are failing today's complex IC designs, which require a proactive, early-stage analysis approach. A shift-left methodology addresses IP block integration challenges and the limitations of traditional simulation and ERC tools. Insight Analyzer detects hard-to-find leakage issues across power domains, enabling early analysis without full simulation. Identify inefficiencies earlier to reduce rework, improve reliability, and enhance power performance.

Click to read more!

featured chalk talk

mPOWER® Ultra Micro Power Connectors
Sponsored by Mouser Electronics and Samtec
In this episode of Chalk Talk, Matt Burns from Samtec and Amelia Dalton explore the key features and benefits of Samtec’s mPOWER Ultra Micro Power Connectors, how they simplify power architecture, and where they fit in today’s evolving design landscape—from data centers and industrial systems to advanced computing and beyond.
May 20, 2026
738 views