editor's blog
Subscribe Now

An Easier-To-Build Unreleased Oscillator

MEMS technology is providing new ways to generate reliable frequencies that conventionally require bulky LC tanks and crystals. Granted, it’s early days (as other monolithic ideas are commercialized), but research proceeds apace, with bulk acoustic wave (BAW) technology now being added to the use of actual mechanical moving parts as candidates for commercialization.

The challenge with an approach requiring a moving part can be summed up in one word: release. While release is required for most MEMS, it’s always extra work to do, and avoiding it is tempting. The alternative to a moving mass is the use of waves transported in a solid, which is the BAW approach. The simplest such device involves two reflectors, top and bottom, but that involves back- and front-side etching.

So-called Bragg reflectors* eliminate the need for so-called “free surface” reflectors by using an sequence of two materials with different acoustic velocities. You typically have them alternating at quarter-wavelength distances, and, if you have enough layers, it acts like a reflector. This can be used at the bottom, for instance, to eliminate the need for all the backside work to get a “real” reflector in there. This is built using alternating thin films in a stack.

In that configuration, the waves travel vertically; there have also been attempts to do this laterally, some of which have challenges and some of which still require release. But a paper at IEDM takes a slightly different approach, using deep-trench capacitors to create the Bragg reflectors and the drive and sense elements.

The good news is that the spacing of the trenches can establish the frequency – that is, lithography provides flexible target frequency design (as opposed to having to rely on a deposited film thickness or etch depth). However, quality is somewhat traded off for manufacturability in that the spacing doesn’t necessarily follow the ideal quarter-wavelength target.

The other piece of good news is, of course, that the manufacturing steps are common for creating shallow-trench isolation (STI) on ICs. (I know, there’s the obvious question: make up your mind, is it deep trench or shallow trench? I guess that, by capacitor standards, it’s a deep trench; by isolation standards, it’s a shallow trench.)

Despite this tradeoff, the researchers claimed that their 3.3-GHz resonator, built on an IBM 32-nm SOI technology, approached the performance of similar suspended-mass resonators. If you have the IEDM proceedings, you can find the details in paper # 15.1.

 

*If you’re unfamiliar with Acoustic Bragg Reflectors, as I was, and want to Google it, be aware… most useful information appears to be locked behind the infamous pay walls. There were some bits and pieces I could salvage, but apparently such knowledge isn’t for us, the hoi polloi…

Leave a Reply

featured blogs
Nov 27, 2023
Most design teams use the schematic-driven connectivity-aware environment of Virtuoso Layout XL. However, due to the reuse of legacy designs, third-party tools, and the flexibility of the Virtuoso platform, a design can lose binding and connectivity. Despite the layout being ...
Nov 27, 2023
Qualcomm Technologies' SVP, Durga Malladi, talks about the current benefits, challenges, use cases and regulations surrounding artificial intelligence and how AI will evolve in the near future....
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines. Also join us for a webinar on the future of the Programmable Solution Group.

Register now: intel.com/leap

featured chalk talk

Stepper Motor Basics & Toshiba Motor Control Solutions
Sponsored by Mouser Electronics and Toshiba
Stepper motors offer a variety of benefits that can add value to many different kinds of electronic designs. In this episode of Chalk Talk, Amelia Dalton and Doug Day from Toshiba examine the different types of stepper motors, the solutions to drive these motors, and how the active gain control and ADMD of Toshiba’s motor control solutions can make all the difference in your next design.
Sep 29, 2023
7,128 views