editor's blog
Subscribe Now

Nanowire Advancements

Nanowires are a perennial IEDM topic, and this year was no exception. Three papers in particular were identified as standing out.

One of them relates to efforts to work germanium into the mix for pFETs. Such work is all about mobility, and a team from MIT achieved twice the mobility of biaxially-strained planar Si. This was done using biaxially-strained germanium that was then patterned into wires using e-beam lithography, which relaxed the lateral strain. The result wasn’t uniaxial strain, but asymmetric. HfO2 was used as the high-κ dielectric, which also acted as an etch-stop when the nanowires are being formed as well as passivation for the Ge/dielectric interface.

A team at Purdue, meanwhile, investigated III-V nanowires for nFETs using InGaAs. They used 20-nm nanowires that were actually a sandwich of In0.53Ga0.47As between In0.65Ga0.35As for higher mobility and lower interface defect density.

They ran three different gate stacks. Two of them used 0.5 nm Al2O3 and 4 nm LaAlO3, with one reversing the order of the stack as compared to the other; this was surrounded by WN. The EOT* of these was 1.2 nm. The other “stack” was simply 3.5 nm of Al2O3 (andthe WN); it had an EOT of 1.7 nm.

The resulting structures exhibited a subthreshold slope (SS) of 63 mV/dec and DIBL of 7 mV/V; Ion was a strong 0.63 mA/µm and gm was 1.74 mS/µm. The SS and gm are the best yet reported; short-channel effects were negligible.

Finally, a team at the Swiss Federal Institute of Technology in Lausanne (EPFL) experimented with ambipolar nanowire structures – devices that can be switched in real time to behave as n-type or p-type. While seen as an annoyance conventionally, this project leveraged the phenomenon by creating a “stack” of four nanowires vertically (using DRIE) and then forming two gates. In the center of the wire was the “standard” control gate; contacting both ends near the source and drain was the polarity gate.

The critical thing about this was that the voltages used to control the two gates were roughly the same. This creates the potential for using both gates in logic designs, the natural function being the XOR gate (with echoes of using MRAM cells as XOR gates). It’s suggested that using XOR gates instead of inverters/NAND/NOR gates can reduce the resources required, although obviously the basic logic math changes due to the different primitive function.

If you have the proceedings, the MIT paper is #16.5; the Purdue paper is #27.6, and the EPFL paper is #8.4. (Yeah, I know, all different sessions… how things get grouped at IEDM remains a mystery to me, but it seems to work for them…)

 

*EOT is “equivalent oxide thickness.” The whole idea of high-κ materials is to provide the “reactivity,” if you will, of a super-thin layer of SiO2 without all the electrons tunneling through because it’s so thin. So you get a thicker layer of material that acts like a layer of SiO2 having a thinner EOT. So this allows the thicknesses of different materials to be “normalized” to SiO2-equivalent thicknesses.

Leave a Reply

featured blogs
Sep 21, 2021
Placing component leads accurately as per the datasheet is an important task while creating a package footprint symbol. As the pin pitch goes down, the size and location of the component lead play a... [[ Click on the title to access the full blog on the Cadence Community si...
Sep 21, 2021
Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging. The post High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1 appeared first on From Silicon To Softw...
Sep 18, 2021
Projects with a steampunk look-and-feel incorporate retro-futuristic technology and aesthetics inspired by 19th-century industrial steam-powered machinery....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Silicon Lifecycle Management Paradigm Shift

Sponsored by Synopsys

An end-to-end platform solution, Silicon Lifecycle Management leverages existing, mature, world-class technologies within Synopsys. This exciting new concept will revolutionize the semiconductor industry and how we manage silicon design. For the first time, designers can look inside silicon chip devices from the moment the design is created to the point at which they end their life.

Click here to learn more about Silicon Lifecycle Management

featured paper

3 key design decisions for any desktop 3D printer design

Sponsored by Texas Instruments

Learn about three important design considerations to take your 3D print design to the next level.

Click to read more

featured chalk talk

Automotive Infotainment

Sponsored by Mouser Electronics and KEMET

In today’s fast-moving automotive electronics design environment, passive components are often one of the last things engineers consider. But, choosing the right passives is now more important than ever, and there is an exciting and sometimes bewildering range of options to choose from. In this episode of Chalk Talk, Amelia Dalton chats with Peter Blais from KEMET about choosing the right passives and the right power distribution for your next automotive design.

Click here for more information about KEMET Electronics Low Voltage DC Auto Infotainment Solutions