editor's blog
Subscribe Now

Nanowire Advancements

Nanowires are a perennial IEDM topic, and this year was no exception. Three papers in particular were identified as standing out.

One of them relates to efforts to work germanium into the mix for pFETs. Such work is all about mobility, and a team from MIT achieved twice the mobility of biaxially-strained planar Si. This was done using biaxially-strained germanium that was then patterned into wires using e-beam lithography, which relaxed the lateral strain. The result wasn’t uniaxial strain, but asymmetric. HfO2 was used as the high-κ dielectric, which also acted as an etch-stop when the nanowires are being formed as well as passivation for the Ge/dielectric interface.

A team at Purdue, meanwhile, investigated III-V nanowires for nFETs using InGaAs. They used 20-nm nanowires that were actually a sandwich of In0.53Ga0.47As between In0.65Ga0.35As for higher mobility and lower interface defect density.

They ran three different gate stacks. Two of them used 0.5 nm Al2O3 and 4 nm LaAlO3, with one reversing the order of the stack as compared to the other; this was surrounded by WN. The EOT* of these was 1.2 nm. The other “stack” was simply 3.5 nm of Al2O3 (andthe WN); it had an EOT of 1.7 nm.

The resulting structures exhibited a subthreshold slope (SS) of 63 mV/dec and DIBL of 7 mV/V; Ion was a strong 0.63 mA/µm and gm was 1.74 mS/µm. The SS and gm are the best yet reported; short-channel effects were negligible.

Finally, a team at the Swiss Federal Institute of Technology in Lausanne (EPFL) experimented with ambipolar nanowire structures – devices that can be switched in real time to behave as n-type or p-type. While seen as an annoyance conventionally, this project leveraged the phenomenon by creating a “stack” of four nanowires vertically (using DRIE) and then forming two gates. In the center of the wire was the “standard” control gate; contacting both ends near the source and drain was the polarity gate.

The critical thing about this was that the voltages used to control the two gates were roughly the same. This creates the potential for using both gates in logic designs, the natural function being the XOR gate (with echoes of using MRAM cells as XOR gates). It’s suggested that using XOR gates instead of inverters/NAND/NOR gates can reduce the resources required, although obviously the basic logic math changes due to the different primitive function.

If you have the proceedings, the MIT paper is #16.5; the Purdue paper is #27.6, and the EPFL paper is #8.4. (Yeah, I know, all different sessions… how things get grouped at IEDM remains a mystery to me, but it seems to work for them…)

 

*EOT is “equivalent oxide thickness.” The whole idea of high-κ materials is to provide the “reactivity,” if you will, of a super-thin layer of SiO2 without all the electrons tunneling through because it’s so thin. So you get a thicker layer of material that acts like a layer of SiO2 having a thinner EOT. So this allows the thicknesses of different materials to be “normalized” to SiO2-equivalent thicknesses.

Leave a Reply

featured blogs
Jan 22, 2021
Amidst an ongoing worldwide pandemic, Samtec continues to connect with our communities. As a digital technology company, we understand the challenges and how uncertain times have been for everyone. In early 2020, Samtec Cares suspended its normal grant cycle and concentrated ...
Jan 22, 2021
I was recently introduced to the concept of a tray that quickly and easily attaches to your car'€™s steering wheel (not while you are driving, of course). What a good idea!...
Jan 22, 2021
This is my second post about this year's CES. The first was Consumer Electronics Show 2021: GM, Intel . AMD The second day of CES opened with Lisa Su, AMD's CEO, presenting. AMD announced new... [[ Click on the title to access the full blog on the Cadence Community...
Jan 20, 2021
Explore how EDA tools & proven IP accelerate the automotive design process and ensure compliance with Automotive Safety Integrity Levels & ISO requirements. The post How EDA Tools and IP Support Automotive Functional Safety Compliance appeared first on From Silicon...

featured paper

Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy

Sponsored by Cadence Design Systems

With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.

Click here to download the whitepaper

Featured Chalk Talk

DC-DC for Gate Drive Power

Sponsored by Mouser Electronics and Murata

In motor control and industrial applications, semiconductor switches such as IGBTs and MOSFETS of all types - including newer wide-bandgap devices are used extensively to switch power to a load. This makes DC to DC conversion for gate drivers a challenge. In this episode of Chalk Talk, Amelia Dalton chats with John Barnes of Murata about DC to DC conversion for gate drivers for industrial and motor control applications.

More information about Murata Power Solutions MGJ DC/DC Converters: