editor's blog
Subscribe Now

Uniting Balkanized Designs

There used to be a nice, clean division: digital chips were verified using the standard suite of digital verification tools like simulation and formal analysis; analog chips were verified by SPICE (for greatest accuracy). That simplicity is gone based on both the use of digital control of analog blocks and the simple fact that integration is now sweeping analog and digital together more often.

According to Berkeley Design, accuracy and productivity have been hurt by the need for most mixed-signal simulators to translate everything into Verilog-AMS before proceeding. While such translation might be possible, at the very least, it results in machine-generated code that the designer didn’t create, which is therefore much harder to debug and which leaves some accuracy on the table.

They’re touting their new Analog FastSPICE AMS as being able to handle any level of nesting of blocks designed using Verilog-AMS, Verilog-D, Verilog-A, and SPICE (in its various flavors). No translation is done; each section can be handled natively and with “nanometer SPICE accuracy.” They’re claiming both accuracy and productivity benefits from the new tool.

You can find out more in their release

Leave a Reply

featured blogs
Jul 9, 2020
I just read '€œEmpty World'€ by John Christopher, and I'€™m sure you will be as amazed as I to discover that this book has a hint of a sniff of the post-apocalyptic about it....
Jul 9, 2020
It happens all the time. We'€™re online with a designer and we'€™re looking at a connector in our picture search. He says '€œI need a connector that looks just like this one, but '€¦'€ and then he goes on to explain something he needs that'€™s unique to his desig...
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...

Featured Video

Product Update: Advances in DesignWare Die-to-Die PHY IP

Sponsored by Synopsys

Hear the latest about Synopsys' DesignWare Die-to-Die PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces. The IP, available in advanced FinFET processes, addresses the power, bandwidth, and latency requirements of high-performance computing SoCs targeting hyperscale data center, AI, and networking applications.

Click here for more information about DesignWare Die-to-Die PHY IP Solutions

Featured Chalk Talk

Innovative Hybrid Crowbar Protection for AC Power Lines

Sponsored by Mouser Electronics and Littelfuse

Providing robust AC line protection is a tough engineering challenge. Lightning and other unexpected events can wreak havoc with even the best-engineered power supplies. In this episode of Chalk Talk, Amelia Dalton chats with Pete Pytlik of Littelfuse about innovative SIDACtor semiconductor hybrid crowbar protection for AC power lines, that combine the best of TVS and MOV technologies to deliver superior low clamping voltage for power lines.

More information about Littelfuse SIDACtor + MOV AC Line Protection