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Uniting Balkanized Designs

There used to be a nice, clean division: digital chips were verified using the standard suite of digital verification tools like simulation and formal analysis; analog chips were verified by SPICE (for greatest accuracy). That simplicity is gone based on both the use of digital control of analog blocks and the simple fact that integration is now sweeping analog and digital together more often.

According to Berkeley Design, accuracy and productivity have been hurt by the need for most mixed-signal simulators to translate everything into Verilog-AMS before proceeding. While such translation might be possible, at the very least, it results in machine-generated code that the designer didn’t create, which is therefore much harder to debug and which leaves some accuracy on the table.

They’re touting their new Analog FastSPICE AMS as being able to handle any level of nesting of blocks designed using Verilog-AMS, Verilog-D, Verilog-A, and SPICE (in its various flavors). No translation is done; each section can be handled natively and with “nanometer SPICE accuracy.” They’re claiming both accuracy and productivity benefits from the new tool.

You can find out more in their release

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