editor's blog
Subscribe Now

Uniting Balkanized Designs

There used to be a nice, clean division: digital chips were verified using the standard suite of digital verification tools like simulation and formal analysis; analog chips were verified by SPICE (for greatest accuracy). That simplicity is gone based on both the use of digital control of analog blocks and the simple fact that integration is now sweeping analog and digital together more often.

According to Berkeley Design, accuracy and productivity have been hurt by the need for most mixed-signal simulators to translate everything into Verilog-AMS before proceeding. While such translation might be possible, at the very least, it results in machine-generated code that the designer didn’t create, which is therefore much harder to debug and which leaves some accuracy on the table.

They’re touting their new Analog FastSPICE AMS as being able to handle any level of nesting of blocks designed using Verilog-AMS, Verilog-D, Verilog-A, and SPICE (in its various flavors). No translation is done; each section can be handled natively and with “nanometer SPICE accuracy.” They’re claiming both accuracy and productivity benefits from the new tool.

You can find out more in their release

Leave a Reply

featured blogs
Jan 17, 2020
I once met Steve Wozniak, or he once met me (it's hard to remember the nitty-gritty details)....
Jan 17, 2020
[From the last episode: We saw how virtual memory helps resolve the differences between where a compiler thinks things will go in memory and the real memories in a real system.] We'€™ve talked a lot about memory '€“ different kinds of memory, cache memory, heap memory, vi...
Jan 16, 2020
While Samtec started as a connector company with a focus on two-piece, pin-and-socket board stacking systems, High-Speed Board Stacking connectors and High-Speed Cable Assemblies now make up a significant portion of our sales. To support development in this area, in December ...
Jan 16, 2020
Betting on Hydrogen-Powered Cars On-demand DRC within P&R cuts closure time in half for MaxLinear Functional Safety Verification For AV SoC Designs Accelerated With Advanced Tools Automating the pain out of clock domain crossing verification Mentor unpacks LVS and LVL iss...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Click here for more information about DesignWare IP for Automotive