editor's blog
Subscribe Now

More Custom Cores

At DAC, there was a special event for first-time DAC exhibitors to come talk to media folks. Kind of a way for them to get better visibility. One company in particular caught my eye – a small firm called Esencia. They’ve announced their EScala Design Platform.

It’s actually reminiscent of Target Compiler, which we covered about a year ago in a piece on multicore automation. The idea is that they analyze a C or C++ algorithmic program (that is, not C specifically structured for high-level synthesis) and then implement a custom architecture. They make use of the OpenRISC ISA, but then partition data flows, merge instructions, create custom instructions, and try to remove instructions if necessary.

They say they could also target a MIPS architecture because it’s standard RISC; ARM is less easy. But they’re not really looking in that direction because their interest lies in deeply-embedded algorithms that don’t need a full-up processor (while at the same time claiming to outperform those same processors).

Much of where they seem to have spent their attention is on moving data around: memory management and I/O bandwidth. For instance, they can do 32 32-bit datapaths (and make it look like a 1024-bit memory).

Their focus has been on multiple data flows for a single core, but claim to be multicore-capable as well.

Their actual tools are cloud-based (although they can do custom installations). The GUI runs on Flash within a browser, although they also have a command-line mode.

You can find more at their website

Leave a Reply

featured blogs
Jan 27, 2021
Why is my poor old noggin filled with thoughts of roaming with my friends through a post-apocalyptic dystopian metropolis ? Well, I'€™m glad you asked......
Jan 27, 2021
Here at the Cadence Academic Network, it is always important to highlight the great work being done by professors, and academia as a whole. Now that AWR software solutions is a part of Cadence, we... [[ Click on the title to access the full blog on the Cadence Community site...
Jan 27, 2021
Super-size. Add-on. Extra. More. We see terms like these a lot, whether at the drive through or shopping online. There'€™s always something else you can add to your order or put in your cart '€“ and usually at an additional cost. Fairly certain at this point most of us kn...
Jan 27, 2021
Cloud computing security starts at hyperscale data centers; learn how embedded IDE modules protect data across interfaces including PCIe 5.0 and CXL 2.0. The post Keeping Hyperscale Data Centers Safe from Security Threats appeared first on From Silicon To Software....

featured paper

Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy

Sponsored by Cadence Design Systems

With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.

Click here to download the whitepaper

Featured Chalk Talk

Bulk Acoustic Wave (BAW) Technology

Sponsored by Mouser Electronics and Texas Instruments

In industrial applications, crystals are not ideal for generating clock signal timing. They take up valuable PCB real-estate, and aren’t stable in harsh thermal and vibration environments. In this episode of Chalk Talk, Amelia Dalton chats with Nick Smith from Texas Instruments about bulk acoustic wave (BAW) technology that offers an attractive alternative to crystals.

More information about Texas Instruments Bulk Acoustic Wave (BAW) Technology