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More Custom Cores

At DAC, there was a special event for first-time DAC exhibitors to come talk to media folks. Kind of a way for them to get better visibility. One company in particular caught my eye – a small firm called Esencia. They’ve announced their EScala Design Platform.

It’s actually reminiscent of Target Compiler, which we covered about a year ago in a piece on multicore automation. The idea is that they analyze a C or C++ algorithmic program (that is, not C specifically structured for high-level synthesis) and then implement a custom architecture. They make use of the OpenRISC ISA, but then partition data flows, merge instructions, create custom instructions, and try to remove instructions if necessary.

They say they could also target a MIPS architecture because it’s standard RISC; ARM is less easy. But they’re not really looking in that direction because their interest lies in deeply-embedded algorithms that don’t need a full-up processor (while at the same time claiming to outperform those same processors).

Much of where they seem to have spent their attention is on moving data around: memory management and I/O bandwidth. For instance, they can do 32 32-bit datapaths (and make it look like a 1024-bit memory).

Their focus has been on multiple data flows for a single core, but claim to be multicore-capable as well.

Their actual tools are cloud-based (although they can do custom installations). The GUI runs on Flash within a browser, although they also have a command-line mode.

You can find more at their website

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