editor's blog
Subscribe Now

Constraining Big Designs

It’s been a while since we took a look at timing constraints (and, in particular, their exceptions). In fact, the exceptions are where things often go wrong. Yes, a constraint may be placed, for example, on the wrong phase of the clock. Presumably, there are plenty of ways to get actual constraints wrong. But exceptions, well, they’re not quite as intuitive.

–          You might think a particular path should be an exception – when, in fact, it matters.

–          You might place an exception on a path that would have been ignored already by the tool for other reasons.

–          You might place several exceptions without realizing that they end up being redundant.

These last couple are particularly pernicious in that they clutter the design with unneeded constraints, slowing things down.

And performance is already an issue what with the size of today’s designs.

This is what Ausdia has set out to address with their new Timevision constraint automation tool. They say that they can generate and verify constraints for an entire SoC either at the RTL level (preferably) or at the gate level (for that unfortunate ECO).

The goal is to improve static timing analysis (STA) by improving the quality of constraints, and doing that in an automatic fashion. But they actually incorporate an STA engine into their own tool, so performance is critical for them as well. They claim faster speed than current solutions based on a couple of angles:

–          They use multi-threading, which gets them close to linear improvement. This brings them 5-15x performance (presumably with up to 16 cores).

–          They also talk about other optimizations… well, they talk about the fact that they exist, but… they don’t actually talk about them because they’re secret. These get them to the 50-100x performance improvement range.

They claim to have had success on designs with as many as 150 million instances and over 5000 clocks, on technologies from 90 nm down to 28 nm.

You can find out more in their release.

Leave a Reply

featured blogs
Sep 23, 2020
CadenceLIVE 2020 India, our first digital conference held on 9-10 September and what an event it was! With 75 technical paper presentations, four keynotes, a virtual exhibition area, and fun... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Sep 22, 2020
If you are at all interested in digital signal processing (DSP), then the DSP Online Conference is the place to '€œsee and be seen'€ -- register now before all the good seats are snapped up!...
Sep 22, 2020
I am a child of the 80s.  I grew up when the idea of home computing was very new.  My first experience of any kind of computer was an Apple II that my Dad brought home from work. It was the only computer his company possessed, and every few weeks he would need to cr...
Sep 18, 2020
[From the last episode: We put the various pieces of a memory together to show the whole thing.] Before we finally turn our memory discussion into an AI discussion, let'€™s take on one annoying little detail that I'€™ve referred to a few times, but have kept putting off. ...

Featured Video

AI SoC Chats: IP for In-Memory / Near-Memory Compute

Sponsored by Synopsys

AI chipsets are data hungry and have high compute intensity, leading to potential power consumption issues. Join Synopsys Fellow Jamil Kawa to learn how in-memory or near-memory compute, 3D stacking, and other innovations can address the challenges of making chips think like the human brain.

Click here for more information about DesignWare IP for Amazing AI

Featured Paper

An Introduction to Automotive LIDAR

Sponsored by Texas Instruments

This white paper is an introduction to industrial and automotive time-of-flight (ToF) light detection and ranging (LIDAR) solutions to serve next-generation autonomous systems.

Click here to download the whitepaper

Featured Chalk Talk

Rail Data Connectivity

Sponsored by Mouser Electronics and TE Connectivity

The rail industry is undergoing a technological revolution right now, and Ethernet connectivity is at the heart of it. But, finding the right interconnect solutions for high-reliability applications such as rail isn’t easy. In this episode of Chalk Talk, Amelia Dalton chats with Egbert Stellinga from TE Connectivity about TE’s portfolio of interconnect solutions for rail and other reliability-critical applications.

Click here for more information about TE Connectivity EN50155 Managed Ethernet Switches