It’s been a while since we took a look at timing constraints (and, in particular, their exceptions). In fact, the exceptions are where things often go wrong. Yes, a constraint may be placed, for example, on the wrong phase of the clock. Presumably, there are plenty of ways to get actual constraints wrong. But exceptions, well, they’re not quite as intuitive.
– You might think a particular path should be an exception – when, in fact, it matters.
– You might place an exception on a path that would have been ignored already by the tool for other reasons.
– You might place several exceptions without realizing that they end up being redundant.
These last couple are particularly pernicious in that they clutter the design with unneeded constraints, slowing things down.
And performance is already an issue what with the size of today’s designs.
This is what Ausdia has set out to address with their new Timevision constraint automation tool. They say that they can generate and verify constraints for an entire SoC either at the RTL level (preferably) or at the gate level (for that unfortunate ECO).
The goal is to improve static timing analysis (STA) by improving the quality of constraints, and doing that in an automatic fashion. But they actually incorporate an STA engine into their own tool, so performance is critical for them as well. They claim faster speed than current solutions based on a couple of angles:
– They use multi-threading, which gets them close to linear improvement. This brings them 5-15x performance (presumably with up to 16 cores).
– They also talk about other optimizations… well, they talk about the fact that they exist, but… they don’t actually talk about them because they’re secret. These get them to the 50-100x performance improvement range.
They claim to have had success on designs with as many as 150 million instances and over 5000 clocks, on technologies from 90 nm down to 28 nm.
You can find out more in their release.