editor's blog
Subscribe Now

A Buttable X-Ray Detector

Most image sensors receive light that has passed through a lens of some sort. This means that a large area can be photographed, for example, and sensed on a chip that is extremely small by comparison with the scene itself.

Not so with medical X-ray imaging. The target sensor gets a full-sized image. Not so hard for dental work, but more challenging for mammography or other full- or partial-body scans.

It’s typically hard, therefore, to provide a solid-state target that can provide seamless coverage. No matter how large they’ve been, they’ve had pixel addressing circuitry on two sides, meaning that you can’t tile them together. (At least not without having “blind stripes” where the decode logic blocks meet up…)

TowerJazz and Tanner worked together with the UK Science and Technology Facility Council’s Rutherford Appleton Labs to develop a unique decoding scheme that allowed them to restrict themselves to only one edge for the circuitry, allowing pixels all the way up to the other three edges. That means that you can tile them in any 2xN configuration.

With each sensor being basically the size of a 200-mm wafer (6.7 Mpixels), they can handle mammography applications with a 2×2 arrangement; longer targets are possible for other applications.

As to how they did the decoding? Yeah… they’re being coy about that. It seems to be largely an analog approach, which is where Tanner contributed to the process. But more details weren’t forthcoming…

You can read more in their release.

EDAS0088-STFCimagesensor_550px.jpg

Leave a Reply

featured blogs
Jan 21, 2022
Here are a few teasers for what you'll find in this week's round-up of CFD news and notes. How AI can be trained to identify more objects than are in its learning dataset. Will GPUs really... [[ Click on the title to access the full blog on the Cadence Community si...
Jan 20, 2022
High performance computing continues to expand & evolve; our team shares their 2022 HPC predictions including new HPC applications and processor architectures. The post The Future of High-Performance Computing (HPC): Key Predictions for 2022 appeared first on From Silico...
Jan 20, 2022
As Josh Wardle famously said about his creation: "It's not trying to do anything shady with your data or your eyeballs ... It's just a game that's fun.'...

featured video

AI SoC Chats: Understanding Compute Needs for AI SoCs

Sponsored by Synopsys

Will your next system require high performance AI? Learn what the latest systems are using for computation, including AI math, floating point and dot product hardware, and processor IP.

Click here for more information about DesignWare IP for Amazing AI

featured paper

nanoPower Module Extends Battery Life in Space-Constrained Applications

Sponsored by Analog Devices

Designers can now increase battery life and reduce size in space-constrained IoT devices with a power module that features the lowest quiescent current compared to competitive solutions and uSLIC built-in inductor technology that reduces solution size by up to 37%.

Read Now

featured chalk talk

SN1000 SmartNIC

Sponsored by Xilinx

Cloud providers face a variety of challenges with moving data from one place to another. In modern data centers, flexibility is a key consideration - on par with performance. Software-defined hardware acceleration offers a major breakthrough in flexibility. In this episode of Chalk Talk, Amelia Dalton chats with Kartik Srinivasan of Xilinx about the details of Smart NICs with the new Alveo SN1000 with composable hardware.

Click here for more information about the Alveo SN1000 - The Composable SmartNIC