editor's blog
Subscribe Now

Optimizing Power at the Architecture Level

When Mentor handed their flagship HLS product, Catapult C, to Calypto almost a year ago, there were a lot of questions about the move. There could be technical, financial, personnel, all kinds of reasons.

Well, at least from a technical standpoint, Calypto just announced what they say was the driving factor: the natural synergy between Catapult C and the Calypto tools. In particular, their PowerPro tool, used for optimizing power.

Automated power optimization typically happens at a low level – typically using netlists (although analysis is moving up to the RTL level). But the real gains are to be had at the architectural level, which is far above RTL even. It’s the realm of untimed C/C++ and SystemC. It’s also the realm of HLS (high-level synthesis, more or less used synonymously with electronic system-level, or ESL). Which is where Catapult C plays.

So they’ve put the two together in a product they’re calling Catapult LP. While the standard Catapult SL can optimize area and performance, it can’t optimize power along with it. Catapult LP does all three by integrating PowerPro under the hood so that it can go figure out what the power will be for a given configuration.

Of course, in order for this to work, Catapult C has to generate RTL out of the high-level code, and then  that RTL has to be synthesized into gates for the low-level power work. Calypto actually has their own RTL synthesis engine which they say can match Synopsys DC results within 15%, which is close enough for architectural level estimation. Yes, they are tracking a tool that’s out of their control, but, realistically, Synopsys isn’t changing DC much these days, so it’s unlikely that there will be much work trying to keep up with the Synopsys updates.

So the designer can create one or more architectural configurations and then have the tool go figure out which one has the lowest power. While the RTL is synthesized in a feed-forward manner for area and performance based on constraints, the power element is managed in a feedback manner.  The gate-level representation can be optimized for clock gating etc. so that those effects can be included in the power estimate, but, at a high level, the designer generates the different options and then selects the one that’s lowest power (of the ones that meet the other constraints). The designer can influence the accuracy and run time through what Calypto calls an “elastic engine” that can be set to select either bit-level or word-level solvers, the former being more accurate but slower.

You can find more information in their release.

Leave a Reply

featured blogs
Jul 12, 2024
I'm having olfactory flashbacks to the strangely satisfying scents found in machine shops. I love the smell of hot oil in the morning....

featured video

Larsen & Toubro Builds Data Centers with Effective Cooling Using Cadence Reality DC Design

Sponsored by Cadence Design Systems

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

Click here for more information about Cadence Multiphysics System Analysis

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured chalk talk

TE Connectivity MULTIGIG RT Connectors
In this episode of Chalk Talk, Amelia Dalton and Ryan Hill from TE Connectivity explore the benefits of TE’s Multigig RT Connectors and how these connectors can help empower the next generation of military and aerospace designs. They examine the components included in these solutions and how the modular design of these connectors make them a great fit for your next military and aerospace design.
Mar 19, 2024
16,098 views