editor's blog
Subscribe Now

Cadence Supports NVMe

Last year, a new standard was overlaid on PCI Express (PCIe) to reset the way non-volatile memory (NVM) is accessed. To date, solid-state disk (SSD) access methodologies had been modeled around the existing mechanisms and limitations surrounding “spinning media” – hard drives. As solid-state memories start to proliferate in roles that used to be dominated by hard drives, those limitations and mechanisms change.

The new standard that accomplishes this is called NVM Express (NVMe), and it uses the basics of PCIe to handle moving the data around, since that’s often how these memory subsystems are connected to the CPU subsystem. But the higher layer adapts PCIe to a specific NVM context.

The standard sets up submission and completion queues – up to 64K of them, each of which can hold up to 64K 64-byte commands. Features include:

  • End-to-end data protection
  • No uncacheable memory-mapped I/O register reads in either the submission or completion path
  • No more than one memory-mapped I/O write to submit a command
  • Queue priority and arbitration
  • Ability to do a 4K-byte read in a single 64-byte command
  • A small basic command set (Read, Write, Write Uncorrectable, Flush, Compare, Dataset Mgmt)
  • Support for interrupt aggregation (including message-signaled interrupts)
  • Multiple namespaces – a device can be decoupled from a “volume”
  • Support for I/O virtualization (like SR-IOV)
  • Error reporting and management
  • Ability to support low-power modes

There are register sets for:

  • Declaring what a particular controller supports
  • Device failure status
  • Configuring an admin queue for managing I/O queues
  • Doorbell registers for submission and completion queues

Cadence just announced their NVMe IP offering, which is based on their existing PCIe IP; the NVMe layer is new, along with the firmware needed to support it. They’ve optimized the underlying PCIe implementation for this particular context, making the overall implementation smaller. They’ve merged the APIs up to the top level so that there is one interface regardless of which layer might be accessed by any given operation. They’ve also coordinated their DMAs for smoother operation and less contention.

They’ve hardware-accelerated the basic commands; the command set itself can be extended through the firmware.

The PCIe PHY is hard IP; the rest is RTL and firmware. They’ve got a tool to configure the IP via an XML description that describes the configuration to their implementation tools.

You can find out more about Cadence’s NVMe IP in their announcement.

Leave a Reply

featured blogs
Apr 13, 2021
We explain the NHTSA's latest automotive cybersecurity best practices, including guidelines to protect automotive ECUs and connected vehicle technologies. The post NHTSA Shares Best Practices for Improving Autmotive Cybersecurity appeared first on From Silicon To Software....
Apr 13, 2021
If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Apr 12, 2021
The Semiconductor Ecosystem- It is the definition of '€œHigh Tech'€, but it isn'€™t just about… The post Calibre and the Semiconductor Ecosystem appeared first on Design with Calibre....
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...

featured video

The Verification World We Know is About to be Revolutionized

Sponsored by Cadence Design Systems

Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.

Click here for more information

featured paper

Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500

Sponsored by Texas Instruments

Functional safety standards such as IEC 61508 and ISO 26262 require semiconductor device manufacturers to address both systematic and random hardware failures. Base failure rates (BFR) quantify the intrinsic reliability of the semiconductor component while operating under normal environmental conditions. Download our white paper which focuses on two widely accepted techniques to estimate the BFR for semiconductor components; estimates per IEC Technical Report 62380 and SN 29500 respectively.

Click here to download the whitepaper

featured chalk talk

Microwave/Millimeter Cable Assemblies and Interconnects

Sponsored by Mouser Electronics and Samtec

Cabling and connectors for RF design are critical to performance. And, in the world of microwave and millimeter-wave design, choosing the right interconnect for your frequency band is key to signal integrity. In this episode of Chalk Talk, Amelia Dalton chats with Matthew Burns of Samtec about what you need to know to choose the right interconnect solution for your next RF design.

Click here for more information about Samtec Precision RF Connectors & Cable Assemblies