editor's blog
Subscribe Now

Powering Up Power Analysis

Apache has just released their latest RedHawk version, RedHawk-3DX. In it they’ve focused on areas of growing importance for power: 3D ICs, working at the RTL level, and scaling up the size of sub-20-nm designs.

Power is of particular concern for 3D ICs because of the fact that a “cube” of silicon is much harder to cool than a plane. And it’s not a monolithic cube; it’s a bunch of interconnected planes that can become detached if you’re not careful. Even the TSVs can be problematic.

They’ve allowed concurrent analysis of each die and the interconnects and TSVs, with the ability to view each piece separately to see where the hot spots and physical stresses are. And they’re not just calculating heat or power; they are determining physical stresses as well. They do this with models, not with full finite-element (FE) analysis, although the models themselves may be created through more accurate FE methods.

RTL-level analysis is important for debug reasons. Most analysis is now done at the gate level, but most designers won’t have vectors at the gate level; only at the RTL level. And if problems are found at the gate level, it’s hard to debug them since that’s not the level designers work at.

So they now have the logic propagation technology in place to support RTL-level analysis with vector inputs. Vectorless analysis is also possible at the RTL and global levels; this is where you specify approximate transition frequencies on pins, and then probabilities (instead of actual events) are propagated to perform the analysis.

For scaling purposes, they have enabled hierarchical analysis, allowing different blocks to be analyzed independently, creating something akin to a bus-function model, where the periphery of the block is accurate while the internals aren’t. That way you can plug the blocks together to see how they interact and still complete the analysis in a reasonable time. A full chip can thus be analyzed with blocks done with or without vectors, at the gate or RTL level; you can mix and match.

There are lots of other details that you can get to via their announcement.

Leave a Reply

featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....

featured video

How NV5, NVIDIA, and Cadence Collaboration Optimizes Data Center Efficiency, Performance, and Reliability

Sponsored by Cadence Design Systems

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Click here for more information about Cadence Data Center Solutions

featured chalk talk

It’s the little things that get you; Light to Voltage Converters
In this episode of Chalk Talk, Amelia Dalton and Ed Mullins from Analog Devices chat about the what, where, and how of photodiode amplifiers. They discuss the challenges involved in designing these kinds of components, the best practices for analyzing the stability of photodiode amplifiers, and how Analog Devices can help you with your next photodiode amplifier design.
Apr 22, 2024
13,556 views