editor's blog
Subscribe Now

Letting Architects Take the Heat

We’re used to seeing a lot more about power and thermal modeling and analysis these days. So perhaps it’s no surprise to see another company making a thermal modeling announcement.

But is Docea’s thermal modeling tool just more of the same? Actually, by their claim, no; it’s unique. And that’s because it works at the architectural level.

Most thermal analysis tools work with finite element analysis or compact thermal models, calculating in detail how much heat there is and where it’s going. Those are typically very specialized tools requiring engineers well grounded in thermal dynamics.

But we all know that the decisions having the most impact on power (and, hence, heat) are made early on when the architecture is set. At that point, the architect is trying to play with high-level blocks, toying with various alternatives to figure out what the best tradeoffs are. At that stage of the design, a thermal guy isn’t going to be satisfied with the level of information available to do any analysis, and, more importantly, if an architect has to hand the design off to a thermal guy for each new idea or configuration, well, that’s going to take forever.

Docea’s approach is intended to allow a non-specialist (thermally speaking, that is) to estimate power at a high level. This lets the architect do quick what-if scenario calculations on the fly (or at least much faster than involving someone else in the process).

You can find more in their release

Leave a Reply

featured blogs
Nov 30, 2023
No one wants to waste unnecessary time in the model creation phase when using a modeling software. Rather than expect users to spend time trawling for published data and tediously model equipment items one by one from scratch, modeling software tends to include pre-configured...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Achieving Reliable Wireless IoT
Sponsored by Mouser Electronics and CEL
Wireless connectivity is one of the most important aspects of any IoT design. In this episode of Chalk Talk, Amelia Dalton and Brandon Oakes from CEL discuss the best practices for achieving reliable wireless connectivity for IoT. They examine the challenges of IoT wireless connectivity, the factors engineers should keep in mind when choosing a wireless solution, and how you can utilize CEL wireless connectivity technologies in your next design.
Nov 28, 2023
303 views