editor's blog
Subscribe Now

Synthesizing TLM Models

Architectural exploration and design implementation all too often are two separate tasks implemented by two completely separate groups. Once a high-level TLM model has been tested and approved, it goes on the shelf while a designer starts from scratch to generate a synthesizable design.

While this may sound simply wasteful, things aren’t so simple. TLM models are abstract, using busses and transactions. An RTL design has to specific signals at the individual level – the TLM model doesn’t have that, so the TLM model tends not to be particularly useful as a starting see for implementation.

Calypto is trying to address that, as they described in a discussion at DVcon. They’re making available a set of interfaces that can be used at multiple levels of abstraction – and, specifically, which can be used to go from architecture to synthesis. They’re starting with AXI, but plan others.

The tie-in with Mentor here is obvious. First off, you may remember that they bought Mentor’s Catapult C. So they have a stake in the high-level synthesis game now. Second, Mentor has a technology that they call Multi-View that allows a single model to be used and viewed with different levels of abstraction for different purposes.

These technologies converge in this IP announcement. You can find more in their release

Leave a Reply

featured blogs
Oct 27, 2021
ASIC hardware verification is a complex process; explore key challenges and bug hunting, debug, and SoC verification solutions to satisfy sign-off requirements. The post The Quest for Bugs: The Key Challenges appeared first on From Silicon To Software....
Oct 27, 2021
Cadence was recently ranked #7 on Newsweek's Most Loved Workplaces list for 2021 and #17 on Fortune's World's Best Workplaces list. Cadence received top recognition among thousands of other companies... [[ Click on the title to access the full blog on the Cadence Community s...
Oct 20, 2021
I've seen a lot of things in my time, but I don't think I was ready to see a robot that can walk, fly, ride a skateboard, and balance on a slackline....
Oct 4, 2021
The latest version of Intel® Quartus® Prime software version 21.3 has been released. It introduces many new intuitive features and improvements that make it easier to design with Intel® FPGAs, including the new Intel® Agilex'„¢ FPGAs. These new features and improvements...

featured video

Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Processor IP

Sponsored by Synopsys

This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on ARC EV7x processor with DNN engine. It shows 3D boxes rendered onto objects detected in the video frames, enabling the development of driver assistance systems.

Click here for more information

featured paper

How to Double the Battery Life of Your Electrochemical Sensor Using a 1V Op Amp for Longer Runtime

Sponsored by Maxim Integrated (now part of Analog Devices)

In this Design Solution, a novel architecture for powering an ethanol sensor is presented. This architecture uses a MAX40108 1V op amp to extend the battery life by more than 40% by substantially reducing both the standby current and the average current in active mode.

Click to read more

featured chalk talk

Time Sensitive Networking for Industrial Automation

Sponsored by Mouser Electronics and Intel

In control applications with strict deterministic requirements, such as those found in automotive and industrial domains, Time Sensitive Networking offers a way to send time-critical traffic over a standard Ethernet infrastructure. This enables the convergence of all traffic classes and multiple applications in one network. In this episode of Chalk Talk, Amelia Dalton chats with Josh Levine of Intel and Patrick Loschmidt of TTTech about standards, specifications, and capabilities of time-sensitive networking (TSN).

Click here for more information about Intel Cyclone® V FPGAs