editor's blog
Subscribe Now

Synthesizing TLM Models

Architectural exploration and design implementation all too often are two separate tasks implemented by two completely separate groups. Once a high-level TLM model has been tested and approved, it goes on the shelf while a designer starts from scratch to generate a synthesizable design.

While this may sound simply wasteful, things aren’t so simple. TLM models are abstract, using busses and transactions. An RTL design has to specific signals at the individual level – the TLM model doesn’t have that, so the TLM model tends not to be particularly useful as a starting see for implementation.

Calypto is trying to address that, as they described in a discussion at DVcon. They’re making available a set of interfaces that can be used at multiple levels of abstraction – and, specifically, which can be used to go from architecture to synthesis. They’re starting with AXI, but plan others.

The tie-in with Mentor here is obvious. First off, you may remember that they bought Mentor’s Catapult C. So they have a stake in the high-level synthesis game now. Second, Mentor has a technology that they call Multi-View that allows a single model to be used and viewed with different levels of abstraction for different purposes.

These technologies converge in this IP announcement. You can find more in their release

Leave a Reply

featured blogs
Jul 10, 2020
[From the last episode: We looked at the convolution that defines the CNNs that are so popular for machine vision applications.] This week we'€™re going to do some more math, although, in this case, it won'€™t be as obscure and bizarre as convolution '€“ and yet we will...
Jul 10, 2020
I need a problem that lends itself to being solved using a genetic algorithm; also, one whose evolving results can be displayed on my 12 x 12 ping pong ball array....
Jul 9, 2020
It happens all the time. We'€™re online with a designer and we'€™re looking at a connector in our picture search. He says '€œI need a connector that looks just like this one, but '€¦'€ and then he goes on to explain something he needs that'€™s unique to his desig...

Featured Video

Product Update: DesignWare® Foundation IP

Sponsored by Synopsys

Join Prasad Saggurti for an update on Synopsys’ DesignWare Foundation IP, including the world’s fastest TCAMs, widest-voltage GPIOs, I2C & I3C IOs, and LVDS IOs. Synopsys Foundation IP is silicon-proven in 7nm in more than 500,000 customer wafers, and 5nm is in development.

Click here for more information about DesignWare Foundation IP: Embedded Memories, Logic Libraries & GPIO

Featured Chalk Talk

Cloud Computing for Electronic Design (Are We There Yet?)

Sponsored by Cadence Design Systems

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

More information about the Cadence Cloud Portfolio