editor's blog
Subscribe Now

Synthesizing TLM Models

Architectural exploration and design implementation all too often are two separate tasks implemented by two completely separate groups. Once a high-level TLM model has been tested and approved, it goes on the shelf while a designer starts from scratch to generate a synthesizable design.

While this may sound simply wasteful, things aren’t so simple. TLM models are abstract, using busses and transactions. An RTL design has to specific signals at the individual level – the TLM model doesn’t have that, so the TLM model tends not to be particularly useful as a starting see for implementation.

Calypto is trying to address that, as they described in a discussion at DVcon. They’re making available a set of interfaces that can be used at multiple levels of abstraction – and, specifically, which can be used to go from architecture to synthesis. They’re starting with AXI, but plan others.

The tie-in with Mentor here is obvious. First off, you may remember that they bought Mentor’s Catapult C. So they have a stake in the high-level synthesis game now. Second, Mentor has a technology that they call Multi-View that allows a single model to be used and viewed with different levels of abstraction for different purposes.

These technologies converge in this IP announcement. You can find more in their release

Leave a Reply

featured blogs
Jun 2, 2023
Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you'll find a community where employees share their perspectives and experiences. By providing a glimpse of their personal...
Jun 2, 2023
I just heard something that really gave me pause for thought -- the fact that everyone experiences two forms of death (given a choice, I'd rather not experience even one)....
Jun 2, 2023
Explore the importance of big data analytics in the semiconductor manufacturing process, as chip designers pull insights from throughout the silicon lifecycle. The post Demanding Chip Complexity and Manufacturing Requirements Call for Data Analytics appeared first on New Hor...

featured video

Automatically Generate, Budget and Optimize UPF with Synopsys Verdi UPF Architect

Sponsored by Synopsys

Learn to translate a high-level power intent from CSV to a consumable UPF across a typical ASIC design flow using Verdi UPF Architect. Power Architect can focus on the efficiency of the Power Intent instead of worrying about Syntax & UPF Semantics.

Learn more about Synopsys’ Energy-Efficient SoCs Solutions

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

Challenges of Multi-Connectivity Asset Tracking
Multi-connectivity asset tracking is a critical element of our modern supply chain. In this episode of Chalk Talk, Colin Ramrattan and Manuel Cantone from STMicroelectronics and Amelia Dalton discuss the common needs required for asset tracking today, why low power processing is vital for these kind of applications, and how STMicroelectronics ASTRA platform can help you get started on your next asset tracking design.
Feb 20, 2023
13,363 views