As SoC designs have ballooned in size and scope, so has the effort required to verify them. A big part of what makes such large designs possible is the use of IP, especially for complex protocols. So that IP needs to play into the verification of the SoC.
But, while IP has raised the level of abstraction for design, it has lagged behind in verification. As Synopsys sees it, even just the complexity of design that’s now possible has driven up the verification burden tremendously due to what is now a scenario count twenty times higher than in the past.
Two of the biggest challenges are straightforward: the amount of time it takes to run all that verification and the ability to debug any issues uncovered during the run.
Performance is hampered first off by the sheer number of lines of VIP code to be run, which Synopsys puts at over 3 million. But making things worse is the fact that the various IP blocks may have verification models that use different languages or base classes, and therefore have to be stitched into the design with wrappers or gaskets. And those can kill performance.
From a debug standpoint, even though we have higher design abstraction, most debug tools operate at a low level so that all of that abstraction is lost.
Synopsys is addressing this with a couple major releases. First is what they call their Discovery VIP platform. The idea is that, with a new underlying architecture and all-SystemVerilog approach, all of the pieces can be stitched together without the need for any intervening adaptation bits. They support the three main verification methodologies, VMM, UVM, and OVM; compile-time switches let you choose which base classes to compile in.
They claim that they get a 4x verification performance benefit from this.
From a debug standpoint, they’ve also announced Protocol Analyzer, a high-level simulation results viewer that takes a verbose simulation log and presents the results in a manner that reflect the context and semantics of a specific piece of IP. So rather than just seeing network traffic as bits, for example, you can see them as packets and even track independent flows. They’ve announced that their tool will work with SpringSoft’s Verdi debugger as well.