editor's blog
Subscribe Now

Better VIP Performance

As SoC designs have ballooned in size and scope, so has the effort required to verify them. A big part of what makes such large designs possible is the use of IP, especially for complex protocols. So that IP needs to play into the verification of the SoC.

But, while IP has raised the level of abstraction for design, it has lagged behind in verification. As Synopsys sees it, even just the complexity of design that’s now possible has driven up the verification burden tremendously due to what is now a scenario count twenty times higher than in the past.

Two of the biggest challenges are straightforward: the amount of time it takes to run all that verification and the ability to debug any issues uncovered during the run.

Performance is hampered first off by the sheer number of lines of VIP code to be run, which Synopsys puts at over 3 million. But making things worse is the fact that the various IP blocks may have verification models that use different languages or base classes, and therefore have to be stitched into the design with wrappers or gaskets. And those can kill performance.

From a debug standpoint, even though we have higher design abstraction, most debug tools operate at a low level so that all of that abstraction is lost.

Synopsys is addressing this with a couple major releases. First is what they call their Discovery VIP platform. The idea is that, with a new underlying architecture and all-SystemVerilog approach, all of the pieces can be stitched together without the need for any intervening adaptation bits. They support the three main verification methodologies, VMM, UVM, and OVM; compile-time switches let you choose which base classes to compile in.

They claim that they get a 4x verification performance benefit from this.

From a debug standpoint, they’ve also announced Protocol Analyzer, a high-level simulation results viewer that takes a verbose simulation log and presents the results in a manner that reflect the context and semantics of a specific piece of IP. So rather than just seeing network traffic as bits, for example, you can see them as packets and even track independent flows. They’ve announced that their tool will work with SpringSoft’s Verdi debugger as well.

You can find more details in the Discovery VIP and the SpringSoft Verdi collaboration releases…

Leave a Reply

featured blogs
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

3D-IC Design Challenges and Requirements

Sponsored by Cadence Design Systems

While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.

Click to read more

featured chalk talk

How IO-Link® is Enabling Smart Factory Digitization -- Analog Devices and Mouser Electronics
Safety, flexibility and sustainability are cornerstone to today’s smart factories. In this episode of Chalk Talk, Amelia Dalton and Shasta Thomas from Analog Devices discuss how Analog Device’s IO-Link is helping usher in a new era of smart factory automation. They take a closer look at the benefits that IO-Link can bring to an industrial factory environment, the biggest issues facing IO-Link sensor and master designs and how Analog Devices ??can help you with your next industrial design.
Feb 2, 2023
36,483 views