editor's blog
Subscribe Now

Accounting for bondwire effects

It’s ISSCC week, and I got to see some interesting things, some of which go beyond interesting and possibly to significant. My focus was on MEMS, sensors, and emerging technologies. I’ll be following up on a number of bits and bobs here over the next several days.

In the MEMS/sensor realm, as was the case last year (where we did an entire series of sensor articles), the focus at ISSCC was on the conditioning circuits for sensors rather than the sensors themselves. The problems they solve are ever better resolution or accuracy with as little calibration as possible.

Just to start things off, the first of the papers dealt with a source of drift (or extremely low-frequency noise, since it’s reversible) in accelerometers. Most such compensations deal with non-idealities in the sensor or in the conditioning circuits themselves. But this picked on something that you might think would be a complete non-issue: the change in the capacitance contributed by the bond wires connecting the accelerometer sensor to its companion ASIC (given that they’re mostly not collocated on the same silicon) due to mechanical stress and humidity.

The reason you might not consider this to be significant is the simple fact that a packaged part usually has bond wires that are encapsulated in plastic, limiting their movement. In fact someone raised that as a question (since the experiments leading to the paper were done with exposed bond wires that could be manually deflected), and, in fairness, the paper doesn’t address how much deflection might actually be realistic. They do say, however, that a 1-µm deflection can contribute a 14-mG offset (“G” here being the gravity/acceleration G, the kind you “pull,” shown as “mg” in the paper, which looks to me too much like milligrams). A 13-µm deflection takes the offset all the way to the maximum tolerable error of 100 mG.

The other issue is absorption of moisture by the package, which changes the permittivity of the material, and hence the capacitance.

Most other sources of systematic error due to design and production can be calibrated out in the factory. These, however, cannot be. So the paper presents a means of doing this.

The main challenge is isolating only the capacitance of the bond wires and the resulting error. The approach they took was to modulate it up into a region of the spectrum that was within the low-noise portion but outside the operating signal band. They did this by applying a time-varying feedback force, measurements from which allowed them to provide a correction to the error.

A classic accelerator would have two electrostatic elements, one for forcing and one for sensing. But to save space, they (or, at least, this one) had only one. So they had to time-multiplex the correction with the normal operation of the sensor to provide continuous correction.

You can find details of the approach in Paper 11.1.

Leave a Reply

featured blogs
Sep 21, 2023
Wireless communication in workplace wearables protects and boosts the occupational safety and productivity of industrial workers and front-line teams....
Sep 26, 2023
5G coverage from space has the potential to make connectivity to the Internet truly ubiquitous for a broad range of use cases....
Sep 26, 2023
Explore the LPDDR5X specification and learn how to leverage speed and efficiency improvements over LPDDR5 for ADAS, smartphones, AI accelerators, and beyond.The post How LPDDR5X Delivers the Speed Your Designs Need appeared first on Chip Design....
Sep 26, 2023
The eighth edition of the Women in CFD series features Mary Alarcon Herrera , a product engineer for the Cadence Computational Fluid Dynamics (CFD) team. Mary's unwavering passion and dedication toward a career in CFD has been instrumental in her success and has led her ...
Sep 21, 2023
Not knowing all the stuff I don't know didn't come easy. I've had to read a lot of books to get where I am....

Featured Video

Chiplet Architecture Accelerates Delivery of Industry-Leading Intel® FPGA Features and Capabilities

Sponsored by Intel

With each generation, packing millions of transistors onto shrinking dies gets more challenging. But we are continuing to change the game with advanced, targeted FPGAs for your needs. In this video, you’ll discover how Intel®’s chiplet-based approach to FPGAs delivers the latest capabilities faster than ever. Find out how we deliver on the promise of Moore’s law and push the boundaries with future innovations such as pathfinding options for chip-to-chip optical communication, exploring new ways to deliver better AI, and adopting UCIe standards in our next-generation FPGAs.

To learn more about chiplet architecture in Intel FPGA devices visit https://intel.ly/45B65Ij

featured paper

Accelerating Monte Carlo Simulations for Faster Statistical Variation Analysis, Debugging, and Signoff of Circuit Functionality

Sponsored by Cadence Design Systems

Predicting the probability of failed ICs has become difficult with aggressive process scaling and large-volume manufacturing. Learn how key EDA simulator technologies and methodologies enable fast (minimum number of simulations) and accurate high-sigma analysis.

Click to read more

featured chalk talk

High-Voltage Isolation for Robust and Reliable System Operation
In this episode of Chalk Talk, Amelia Dalton and Luke Trowbridge from Texas Instruments examine the benefits of isolation in high voltage systems. They also explore the benefits of TI’s integrated transformer technology and how TI’s high voltage isolations can help you streamline your design process, reduce your bill of materials, and ensure reliable and robust system operation.
Apr 27, 2023
17,493 views