editor's blog
Subscribe Now

Accounting for bondwire effects

It’s ISSCC week, and I got to see some interesting things, some of which go beyond interesting and possibly to significant. My focus was on MEMS, sensors, and emerging technologies. I’ll be following up on a number of bits and bobs here over the next several days.

In the MEMS/sensor realm, as was the case last year (where we did an entire series of sensor articles), the focus at ISSCC was on the conditioning circuits for sensors rather than the sensors themselves. The problems they solve are ever better resolution or accuracy with as little calibration as possible.

Just to start things off, the first of the papers dealt with a source of drift (or extremely low-frequency noise, since it’s reversible) in accelerometers. Most such compensations deal with non-idealities in the sensor or in the conditioning circuits themselves. But this picked on something that you might think would be a complete non-issue: the change in the capacitance contributed by the bond wires connecting the accelerometer sensor to its companion ASIC (given that they’re mostly not collocated on the same silicon) due to mechanical stress and humidity.

The reason you might not consider this to be significant is the simple fact that a packaged part usually has bond wires that are encapsulated in plastic, limiting their movement. In fact someone raised that as a question (since the experiments leading to the paper were done with exposed bond wires that could be manually deflected), and, in fairness, the paper doesn’t address how much deflection might actually be realistic. They do say, however, that a 1-µm deflection can contribute a 14-mG offset (“G” here being the gravity/acceleration G, the kind you “pull,” shown as “mg” in the paper, which looks to me too much like milligrams). A 13-µm deflection takes the offset all the way to the maximum tolerable error of 100 mG.

The other issue is absorption of moisture by the package, which changes the permittivity of the material, and hence the capacitance.

Most other sources of systematic error due to design and production can be calibrated out in the factory. These, however, cannot be. So the paper presents a means of doing this.

The main challenge is isolating only the capacitance of the bond wires and the resulting error. The approach they took was to modulate it up into a region of the spectrum that was within the low-noise portion but outside the operating signal band. They did this by applying a time-varying feedback force, measurements from which allowed them to provide a correction to the error.

A classic accelerator would have two electrostatic elements, one for forcing and one for sensing. But to save space, they (or, at least, this one) had only one. So they had to time-multiplex the correction with the normal operation of the sensor to provide continuous correction.

You can find details of the approach in Paper 11.1.

Leave a Reply

featured blogs
May 25, 2023
Register only once to get access to all Cadence on-demand webinars. Unstructured meshing can be automated for much of the mesh generation process, saving significant engineering time and cost. However, controlling numerical errors resulting from the discrete mesh requires ada...
May 24, 2023
Accelerate vision transformer models and convolutional neural networks for AI vision systems with the ARC NPX6 NPU IP, the best processor for edge AI devices. The post Designing Smarter Edge AI Devices with the Award-Winning Synopsys ARC NPX6 NPU IP appeared first on New Hor...
May 8, 2023
If you are planning on traveling to Turkey in the not-so-distant future, then I have a favor to ask....

featured video

Automatically Generate, Budget and Optimize UPF with Synopsys Verdi UPF Architect

Sponsored by Synopsys

Learn to translate a high-level power intent from CSV to a consumable UPF across a typical ASIC design flow using Verdi UPF Architect. Power Architect can focus on the efficiency of the Power Intent instead of worrying about Syntax & UPF Semantics.

Learn more about Synopsys’ Energy-Efficient SoCs Solutions

featured contest

Join the AI Generated Open-Source Silicon Design Challenge

Sponsored by Efabless

Get your AI-generated design manufactured ($9,750 value)! Enter the E-fabless open-source silicon design challenge. Use generative AI to create Verilog from natural language prompts, then implement your design using the Efabless chipIgnite platform - including an SoC template (Caravel) providing rapid chip-level integration, and an open-source RTL-to-GDS digital design flow (OpenLane). The winner gets their design manufactured by eFabless. Hurry, though - deadline is June 2!

Click here to enter!

featured chalk talk

dsPIC33CH DSCs: Two dsPIC33Cs on a Single Chip
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Vijay Bapu from Microchip and Amelia Dalton explore the benefits of dual core digital signal controllers. They discuss the key specifications to keep in mind when it comes to single core and dual core DSCs and how you can reduce your development time, save board space and cost and keep the performance and isolation you need with Microchip’s dsPIC33CH DSCs.
Jan 24, 2023