editor's blog
Subscribe Now

What Comes Around… Is Reflected?

With higher-frequency (GHz) signals becoming more prevalent on trusty old-school FR-4 boards, it’s become increasingly important to test the quality of the lines – specifically, their insertion loss (SDD21) – as a PCB manufacturing step. The problem is that you have to probe both ends of a trace in order to do this. Not so hard in the lab, but high-volume testers aren’t really built for that – they want to probe in one place.

Two years ago at DesignCon, Intel proposed a new method of determining the insertion loss by taking time-domain measurements at only two points, both at the same end of the line. They called it “Single-Ended TDR to Differential Insertion Loss,” or SET2DIL.

A quick terminology note here: there seems to be inconsistency in the industry about what those test points are called. Some refer to them as two “terminals,” which equate to one “port.” Rhode and Schwartz (and perhaps other) seem to equate “terminal” and “port,” so the kinds of systems we’re talking about here are all four-terminal systems, but may be two-port or four-port systems, depending on your definition of “port.” So the problem being solved here is the ability to test the four-terminal system by measuring only two terminals. And, critically, both of those terminals are at the same end of the two traces that make up the differential pair.

At this year’s DesignCon, SET2DIL appears to be showing up, at least in software form. Rhode and Schwarz was demonstrating, among other things, that their vector network analyzer (VNA) could make the time domain (reflectometry or transmissometry) measurements and then drive them into a computer that ran the SET2DIL algorithm to calculate the differential insertion loss. They say that they’re working to integrate the algorithm into the VNA itself.

Polar Instruments also appears to be supporting SET2DIL in software as of their 2012 Atlas release.

More information on Rhode and Schwarz’s solution can be found in their release.

Leave a Reply

featured blogs
Apr 9, 2021
You probably already know what ISO 26262 is. If you don't, then you can find out in several previous posts: "The Safest Train Is One that Never Leaves the Station" History of ISO 26262... [[ Click on the title to access the full blog on the Cadence Community s...
Apr 8, 2021
We all know the widespread havoc that Covid-19 wreaked in 2020. While the electronics industry in general, and connectors in particular, took an initial hit, the industry rebounded in the second half of 2020 and is rolling into 2021. Travel came to an almost stand-still in 20...
Apr 7, 2021
We explore how EDA tools enable hyper-convergent IC designs, supporting the PPA and yield targets required by advanced 3DICs and SoCs used in AI and HPC. The post Why Hyper-Convergent Chip Designs Call for a New Approach to Circuit Simulation appeared first on From Silicon T...
Apr 5, 2021
Back in November 2019, just a few short months before we all began an enforced… The post Collaboration and innovation thrive on diversity appeared first on Design with Calibre....

featured video

Learn the basics of Hall Effect sensors

Sponsored by Texas Instruments

This video introduces Hall Effect, permanent magnets and various magnetic properties. It'll walk through the benefits of Hall Effect sensors, how Hall ICs compare to discrete Hall elements and the different types of Hall Effect sensors.

Click here for more information

featured paper

Understanding the Foundations of Quiescent Current in Linear Power Systems

Sponsored by Texas Instruments

Minimizing power consumption is an important design consideration, especially in battery-powered systems that utilize linear regulators or low-dropout regulators (LDOs). Read this new whitepaper to learn the fundamentals of IQ in linear-power systems, how to predict behavior in dropout conditions, and maintain minimal disturbance during the load transient response.

Click here to download the whitepaper

featured chalk talk

Accelerating Physical Verification Productivity Part Two

Sponsored by Synopsys

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Click here for more information about Physical Verification using IC Validator