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Engineering GaN Wafers

We talked before about wide bandgap materials such as GaN and SiC, but how are the base wafers for those materials created? Full wafers of expensive material would be, well, expensive. But if you grow or somehow affix the material on a base material of some other sort, you run the risk of having thermal issues at the boundary (at the very least).

Sumitomo and Soitec announced a joint approach recently that provides a GaN layer on top of some other substrate. The key is that this substrate is thermally matched to GaN. Of course, when I inquired as to the nature of the material, I found it was this mystery material that seems to be common to a huge number of projects: the material is called “proprietary.”

The method of creating the GaN on top of this takes a page from how Soitec creates SOI base wafers, with their SmartCut process. If you haven’t heard about it before, it’s interesting. The concept is that, in this case, Sumitomo sends them a pure GaN wafer. Soitec provides the base and then slices off a thin layer of GaN and affixes it to the base wafer. So one GaN wafer gets sliced many many times and ends up serving a large number of actual used wafers, stretching the GaN material as far as it will go.

So you might wonder, how do you slice off such a thin layer? Here’s what they do: first they implant hydrogen into the top of the GaN wafer down to the thickness of the layer they want to cut off. They then turn this wafer upside down and affix it to the base wafer, so now you have two wafers bonded together face-to-face.

They then use heat to create bubbles at the layer where the hydrogen is; this causes cracking along that seam, and the GaN bulk wafer comes off, leaving just the thin layer attached to the new base material. A little spit and polish and you’re good to go.

They had done this with 2” wafers before; their recent announcement demonstrates scaling to 4” and 6” wafers. You can find more in their release.

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