editor's blog
Subscribe Now

Establishing 3D IC Standards – Or Not

For those of you watching 3D IC advancements, there’s a discussion you might want to come join next week at DesignCon in Santa Clara. Bill Bayer and Sumit DasGupta of Si2 have assembled a panel from Qualcomm, Sematech, Si2, and Xilinx, plus Jim Hogan, to discuss what, if anything, needs to be standardized in the 3D IC world in order to help it build a head of steam.

Standards cut both ways. Done well, they reduce chaos and help provide some direction for market participants. This makes folks less cautious about adopting and driving the technology. Too many standards, or the wrong ones, however, and you block the opportunity to do something better because you’ve locked in an old idea as a standard.

And it’s not always easy to find your way through the maze of things that could be standardized, especially once a standards body gets ahold of it. I remember years ago at JEDEC trying to set I/O standards. This was important so that different chips could talk to each other. But those I/O standards are on the datasheet – and the committee just couldn’t stop there and had to start standardizing practically the whole dang datasheet, even though interchange was no longer the issue (and no one had complained about the rest of the datasheet).

Anyway, here’s your opportunity to weigh in. I’ll be seeding the discussion with questions on the off chance that these guys need any prodding. And we’ll also be encouraging audience questions, so come make yourselves heard. We’re on at 3:45 on January 31st. Hope to see you.

More details in the announcement

Leave a Reply

featured blogs
May 7, 2021
In one of our Knowledge Booster Blogs a few months ago we introduced you to some tips and tricks for the optimal use of Virtuoso ADE Product Suite with our analog IC design videos . W e hope you... [[ Click on the title to access the full blog on the Cadence Community site. ...
May 7, 2021
Enough of the letter “P” already. Message recieved. In any case, modeling and simulating next-gen 224 Gbps signal channels poses many challenges. Design engineers must optimize the entire signal path, not just a specific component. The signal path includes transce...
May 6, 2021
Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process. The post Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification appeared first on Fr...
May 4, 2021
What a difference a year can make! Oh, we're not referring to that virus that… The post Realize Live + U2U: Side by Side appeared first on Design with Calibre....

featured video

Introduction to EMI

Sponsored by Texas Instruments

Conducted versus radiated EMI. CISPR-25 and CISPR-32 standards. High-frequency or low-frequency emissions. Designing a system to reduce EMI can be overwhelming, but it doesn’t have to be. Watch this video to get an overview of EMI causes, standards, and mitigation techniques.

Click here for more information

featured paper

Smile, You're on My Security Camera!

Sponsored by Maxim Integrated

Advances in wireless and IoT technologies are fueling market growth for security camera systems. Outdoor security cameras need to operate for a long time on small disposable batteries. This design solution shows how a high-performance power management system can power an outdoor security camera several months longer than an ordinary solution.

Click to read more

Featured Chalk Talk

General Port Protection

Sponsored by Mouser Electronics and Littelfuse

In today’s complex designs, port protection can be a challenge. High-speed data, low-speed data, and power ports need protection from ESD, power faults, and more. In this episode of Chalk Talk, Amelia Dalton chats with Todd Phillips from Littelfuse about port protection for your next system design.

Click here for more information about port protection from Littelfuse.