editor's blog
Subscribe Now

Speeding up FLASH

Most of what you hear about FLASH developments relates to capacity. But bandwidth is becoming more critical as we stream more data around – particularly for applications where FLASH is replacing a hard drive. Yes, FLASH is already faster than a disk, but moving to solid-state storage – especially in growing data-intensive areas like cloud computing – will ramp up expectations on how much we can shove down that poor memory’s throat. Digital fois gras anyone?

At least this is how Cadence sees things happening (well, except for the fois gras part). They’ve just announced support for the higher-speed ONFi 3 interface standard, which revs up access to 400 MT/s –  twice what it used to be. In theory, anyway.

However, they also claim that most implementations of ONFi 3 only achieve 85-90% or so of that theoretical performance. Cadence claims that with their IP portfolio (PHY, controller, ECC), they can achieve 95% of that 400 MT/s.

They’re also touting their ECC – it’s becoming much more important at high densities for both probabilistic and sensing sensitivity reasons. This is especially true with cells that can carry more than one bit’s worth of information: you’re measuring fine gradations of trapped charge, increasing the risk of statistical errors.

Which brings me to my kvetch of the day… terminology. SLC = single-level cell. Your standard, garden-variety memory cell – on or off. One level; one bit; two values. Then there was multi-level cell, or MLC. As far as I was concerned, this was a generic term for anything more than one. “Multi” being rather, well, generic. But no – apparently in this language “multi” means two. Well, actually, that’s not even right. The number of levels in an MLC cell, by this definition, is 4 – there are 4 levels, equivalent to 2 bits’ worth of information.

And then there’s the confusing TLC – three- (or triple-) level cell. Which is doubly confusing since “three” should qualify as part of “multi” since it’s more than one. But it’s worse than that, since a TLC doesn’t have 3 levels – it has 8 levels, 3 bits’ worth of information. Call it a TBC perhaps. Or an ELC. Or an 8LC. TLC is just wrong. And defining “multi” as 2 (or 4) is just goofy.

OK, rant over. More info on Cadence’s announcement is available on their release

Leave a Reply

featured blogs
Sep 28, 2022
Learn how our acquisition of FishTail Design Automation unifies end-to-end timing constraints generation and verification during the chip design process. The post Synopsys Acquires FishTail Design Automation, Unifying Constraints Handling for Enhanced Chip Design Process app...
Sep 28, 2022
You might think that hearing aids are a bit of a sleepy backwater. Indeed, the only time I can remember coming across them in my job at Cadence was at a CadenceLIVE Europe presentation that I never blogged about, or if I did, it was such a passing reference that Google cannot...
Sep 22, 2022
On Monday 26 September 2022, Earth and Jupiter will be only 365 million miles apart, which is around half of their worst-case separation....

featured video

PCIe Gen5 x16 Running on the Achronix VectorPath Accelerator Card

Sponsored by Achronix

In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t FPGA is one of the first FPGAs that can natively support this interface within its PCIe subsystem. Speedster7t FPGAs offer a revolutionary new architecture that Achronix developed to address the highest performance data acceleration challenges.

Click here for more information about the VectorPath Accelerator Card

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Enabling Digital Transformation in Electronic Design with Cadence Cloud

Sponsored by Cadence Design Systems

With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.

Click here for more information about Cadence Cloud Portfolio