editor's blog
Subscribe Now

Speeding up FLASH

Most of what you hear about FLASH developments relates to capacity. But bandwidth is becoming more critical as we stream more data around – particularly for applications where FLASH is replacing a hard drive. Yes, FLASH is already faster than a disk, but moving to solid-state storage – especially in growing data-intensive areas like cloud computing – will ramp up expectations on how much we can shove down that poor memory’s throat. Digital fois gras anyone?

At least this is how Cadence sees things happening (well, except for the fois gras part). They’ve just announced support for the higher-speed ONFi 3 interface standard, which revs up access to 400 MT/s –  twice what it used to be. In theory, anyway.

However, they also claim that most implementations of ONFi 3 only achieve 85-90% or so of that theoretical performance. Cadence claims that with their IP portfolio (PHY, controller, ECC), they can achieve 95% of that 400 MT/s.

They’re also touting their ECC – it’s becoming much more important at high densities for both probabilistic and sensing sensitivity reasons. This is especially true with cells that can carry more than one bit’s worth of information: you’re measuring fine gradations of trapped charge, increasing the risk of statistical errors.

Which brings me to my kvetch of the day… terminology. SLC = single-level cell. Your standard, garden-variety memory cell – on or off. One level; one bit; two values. Then there was multi-level cell, or MLC. As far as I was concerned, this was a generic term for anything more than one. “Multi” being rather, well, generic. But no – apparently in this language “multi” means two. Well, actually, that’s not even right. The number of levels in an MLC cell, by this definition, is 4 – there are 4 levels, equivalent to 2 bits’ worth of information.

And then there’s the confusing TLC – three- (or triple-) level cell. Which is doubly confusing since “three” should qualify as part of “multi” since it’s more than one. But it’s worse than that, since a TLC doesn’t have 3 levels – it has 8 levels, 3 bits’ worth of information. Call it a TBC perhaps. Or an ELC. Or an 8LC. TLC is just wrong. And defining “multi” as 2 (or 4) is just goofy.

OK, rant over. More info on Cadence’s announcement is available on their release

Leave a Reply

featured blogs
Jan 27, 2021
Why is my poor old noggin filled with thoughts of roaming with my friends through a post-apocalyptic dystopian metropolis ? Well, I'€™m glad you asked......
Jan 27, 2021
Here at the Cadence Academic Network, it is always important to highlight the great work being done by professors, and academia as a whole. Now that AWR software solutions is a part of Cadence, we... [[ Click on the title to access the full blog on the Cadence Community site...
Jan 27, 2021
Super-size. Add-on. Extra. More. We see terms like these a lot, whether at the drive through or shopping online. There'€™s always something else you can add to your order or put in your cart '€“ and usually at an additional cost. Fairly certain at this point most of us kn...
Jan 27, 2021
Cloud computing security starts at hyperscale data centers; learn how embedded IDE modules protect data across interfaces including PCIe 5.0 and CXL 2.0. The post Keeping Hyperscale Data Centers Safe from Security Threats appeared first on From Silicon To Software....

featured paper

Overcoming Signal Integrity Challenges of 112G Connections on PCB

Sponsored by Cadence Design Systems

One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).

Click here to download the whitepaper

Featured Chalk Talk

Hello FPGA

Sponsored by Mouser Electronics and Microchip

Getting started on an FPGA-based embedded vision project can be tricky. Locating all the components you need, getting them to talk to each other, and just getting your system to the video equivalent of “Hello World” is a pretty daunting task. In this episode of Chalk Talk, Amelia Dalton chats with Avery Williams of Microchip Technology about the Hello FPGA kit - a low-cost, low-touch embedded vision kit for engineers new to FPGAs.

More information about Microchip Technology Hello FPGA Kit