editor's blog
Subscribe Now

Speeding up FLASH

Most of what you hear about FLASH developments relates to capacity. But bandwidth is becoming more critical as we stream more data around – particularly for applications where FLASH is replacing a hard drive. Yes, FLASH is already faster than a disk, but moving to solid-state storage – especially in growing data-intensive areas like cloud computing – will ramp up expectations on how much we can shove down that poor memory’s throat. Digital fois gras anyone?

At least this is how Cadence sees things happening (well, except for the fois gras part). They’ve just announced support for the higher-speed ONFi 3 interface standard, which revs up access to 400 MT/s –  twice what it used to be. In theory, anyway.

However, they also claim that most implementations of ONFi 3 only achieve 85-90% or so of that theoretical performance. Cadence claims that with their IP portfolio (PHY, controller, ECC), they can achieve 95% of that 400 MT/s.

They’re also touting their ECC – it’s becoming much more important at high densities for both probabilistic and sensing sensitivity reasons. This is especially true with cells that can carry more than one bit’s worth of information: you’re measuring fine gradations of trapped charge, increasing the risk of statistical errors.

Which brings me to my kvetch of the day… terminology. SLC = single-level cell. Your standard, garden-variety memory cell – on or off. One level; one bit; two values. Then there was multi-level cell, or MLC. As far as I was concerned, this was a generic term for anything more than one. “Multi” being rather, well, generic. But no – apparently in this language “multi” means two. Well, actually, that’s not even right. The number of levels in an MLC cell, by this definition, is 4 – there are 4 levels, equivalent to 2 bits’ worth of information.

And then there’s the confusing TLC – three- (or triple-) level cell. Which is doubly confusing since “three” should qualify as part of “multi” since it’s more than one. But it’s worse than that, since a TLC doesn’t have 3 levels – it has 8 levels, 3 bits’ worth of information. Call it a TBC perhaps. Or an ELC. Or an 8LC. TLC is just wrong. And defining “multi” as 2 (or 4) is just goofy.

OK, rant over. More info on Cadence’s announcement is available on their release

Leave a Reply

featured blogs
Jul 25, 2021
https://youtu.be/cwT7KL4iShY Made on "a tropical beach" Monday: Aerospace and Defense Systems Day...and DAU Tuesday: 75 Years of the Microprocessor Wednesday: CadenceLIVE Cloud Panel... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Jul 24, 2021
Many modern humans have 2% Neanderthal DNA in our genomes. The combination of these DNA snippets is like having the ghost of a Neanderthal in our midst....
Jul 23, 2021
Synopsys co-CEO Aart de Geus explains how AI has become an important chip design tool as semiconductor companies continue to innovate in the SysMoore Era. The post Entering the SysMoore Era: Synopsys Co-CEO Aart de Geus on the Need for AI-Designed Chips appeared first on Fro...
Jul 9, 2021
Do you have questions about using the Linux OS with FPGAs? Intel is holding another 'Ask an Expert' session and the topic is 'Using Linux with Intel® SoC FPGAs.' Come and ask our experts about the various Linux OS options available to use with the integrated Arm Cortex proc...

featured video

Design Success with Foundation IP & Fusion Compiler

Sponsored by Synopsys

When is 1+1 greater than 2? When using DesignWare Foundation IP & Fusion Compiler! Join Raymond and Yung in their discussion of a customer that benefited from the combination of Fusion Compiler’s machine learning and Foundation IP cells and macros.

More information about DesignWare Foundation IP: Embedded Memories, Logic Libraries, GPIO & PVT Sensors

featured paper

PrimeLib Next-Gen Library Characterization - Providing Accelerated Access to Advanced Process Nodes

Sponsored by Synopsys

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

Click to read the latest issue of Designer's Digest

Featured Chalk Talk

Digi Remote Manager

Sponsored by Mouser Electronics and Digi

With the complexity of today’s networks, the proliferation of IoT, and the increase in remote access requirements, remote management is going from “nice to have” to “critical” in network design and deployment. In this episode of Chalk Talk, Amelia Dalton chats with Stefan Budricks of Digi International about how Digi Remote Manager can address your remote management and security needs.

Click here for more information about DIGI XBee® Tools