editor's blog
Subscribe Now

Moving Up a Different Channel

LDRA continues to move upstream in the design flow with its certification tools. We saw not long ago that they were interconnecting with Simulink to push testing further up that modeling path; now they’ve announced similar arrangements with National Instruments’ LabView platform.

The idea here is that, when modeling safety-critical systems – especially those that have to pass regulatory muster – you can get a jump start by testing the early snippets of code that might be modeled long before the system starts to come together in a substantial way. In particular, LabView is able to model target hardware in a manner that meets the software testing requirements of DO-178, Level A. This provides more confidence that the code, once tested and clean, will remain clean into the later design and implementation phases.

More info in their release

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Maximizing Power Savings During Chip Implementation with Dynamic Refresh of Vectors

Sponsored by Synopsys

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn more about Energy-Efficient SoC Solutions

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Industrial Ethernet Next Generation Connections

Sponsored by Mouser Electronics and Amphenol ICC

No longer are hierarchical communication models effective in this new era of Industry 4.0. We need to look at an independent communication model that includes a single network with industrial ethernet at its core. In this episode of Chalk Talk, Amelia Dalton chats with Peter Swift about Amphenol’s SPE and iX Industrial family of connectors. They take a closer look at the details of these connector solutions and investigate why they are a great fit for the next generation of industrial automation applications.

Click here for more information about Amphenol ICC Industrial Ethernet Connectors & Cable Assemblies