I should clarify one thing here, since I’ve had some offline correspondence about this. When discussing the use of emulation, I referred to needing it when running the “actual design.”

In my context (or in my mind) I was contrasting that to the architectural level modeling done prior to detailed design.

In other words, you should interpret “actual design” as RTL or gate-level, where the alternative to emulation is simulation (which is problematic when running through billions of cycles).