I/O models have become increasingly important as we’ve moved from dumb 5-V-swing full-rail CMOS I/Os (remember those?) to the tight, sensitive kinds of I/Os needed for serial connections and DDR memory. Along with that we’ve gone from no need for models to the need for very accurate models to ensure that signals will get where they’re going without being swamped by noise.
IBIS models have served that purpose, but they also were pretty rough and ready in their earlier incarnations, requiring manual work to create them.
Sigrity is trying to address this by releasing TB2, a tool that takes a transistor-level design and automatically creates a power-aware IBIS 5.0 model. By starting from the transistor level, the intent is that the model can be much more accurate than what has traditionally been possible.
More info in their release…