editor's blog
Subscribe Now

HLS from Scratch

On the heels of the announcement of an entirely new analog design tool suite comes something else surprising. And I can’t quite figure it out.

I received an “announcement” of a new HLS (i.e., nominally, a C-to-VHDL) tool called HercuLeS. Except that the announcement didn’t read like a commercial launch: it read more like a note to friends and colleagues. It was written by Nikolaos Kavvadian, who describes himself in his email signature as “Lecturer, Research scientist, Hardware developer, Ph.D., M.Sc., B.Sc.”

I followed up with him to clarify whether this was a research effort or a commercial launch. He confirmed that this was developed separately from his academic work, and that it is a commercial, not an academic, venture. But apparently it’s not really commercialized yet: you can get to it online, but there’s a web interface that’s going to be released in October. At that point, the tool will still be available for free for limited programs; the pricing for full-on use hasn’t been set yet.

He doesn’t view HercuLeS competing specifically with the usual EDA suspects (which is mostly Catapult C, since Cadence and Synopsys deal with SystemC, not ANSI C). He sees some niche markets that they’ll be focusing on in Q4, including select supercomputing applications and the FPGA+µP (Altera/Intel, Xilinx/ARM) space.

I asked about quality of results (QoR): it’s relatively straightforward to come up with a model for converting software to hardware; the hard part is doing that efficiently, and the incumbents have years of accumulated QoR improvements under their belts. This sets a really high bar for newcomers to be taken seriously. Dr. Kavvadian acknowledged the importance of QoR, asserting that one main contributor to QoR is the intermediate representation (IR) used.

And this seems to be a key to this technology: it’s focused on GIMPLE, a Gnu set of IRs that have front ends to various languages, and NAC, a low-level language they have defined. The language (ANSI C in this case) is mapped to GIMPLE, and they then map that to NAC. NAC can be extended to provide improved mappings to hardware as experience builds. He sees this, along with optimized implementation of black boxes and their model of computation, as the crucial element.

The IR also unlocks something else they have their eye on: possible support of Python and Go or other languages that can be mapped to GIMPLE. Such users are another possible niche market for them.

All in all, I’m not quite sure what to make of this. It’s clearly very engineering driven, and the “launch” lacks many of the standard business trappings – which may not be a bad thing. Just a confusing thing. The business model – or at least the pricing – still aren’t set, so it’s almost like we’re watching this evolve.

We’ll keep an eye to see what happens. Meanwhile you can check here for more information.

Leave a Reply

featured blogs
May 19, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This... ...
May 19, 2022
Learn about the AI chip design breakthroughs and case studies discussed at SNUG Silicon Valley 2022, including autonomous PPA optimization using DSO.ai. The post Key Highlights from SNUG 2022: AI Is Fast Forwarding Chip Design appeared first on From Silicon To Software....
May 12, 2022
By Shelly Stalnaker Every year, the editors of Elektronik in Germany compile a list of the most interesting and innovative… ...
Apr 29, 2022
What do you do if someone starts waving furiously at you, seemingly delighted to see you, but you fear they are being overenthusiastic?...

featured video

Building safer robots with computer vision & AI

Sponsored by Texas Instruments

Watch TI's demo to see how Jacinto™ 7 processors fuse deep learning and traditional computer vision to enable safer autonomous mobile robots.

Watch demo

featured paper

Reduce EV cost and improve drive range by integrating powertrain systems

Sponsored by Texas Instruments

When you can create automotive applications that do more with fewer parts, you’ll reduce both weight and cost and improve reliability. That’s the idea behind integrating electric vehicle (EV) and hybrid electric vehicle (HEV) designs.

Click to read more

featured chalk talk

Powering Servers and AI with Ultra-Efficient IPOL Voltage Regulators

Sponsored by Infineon

For today’s networking, telecom, server, and enterprise storage applications, power efficiency and power density are crucial components to the success of their power management. In this episode of Chalk Talk, Amelia Dalton and Dr. Davood Yazdani from Infineon chat about the details of Infineon’s ultra-efficient integrated point of load voltage regulators. Davood and Amelia take a closer look at the operation of these integrated point of load voltage regulators and why using the Infineon OptiMOS 5 FETs combined with the Infineon Fast Constant On Time controller engine make them a great solution for your next design.

Click here for more information about Integrated POL Voltage Regulators