editor's blog
Subscribe Now

Your Standard Merger

Last week OSCI and Accellera decided to join forces. To some extent, this might be viewed as the union of the abstract and the concrete. OSCI lives in the world of SystemC and TLM; much of what Accellera does is further down the abstraction stack (although UVM shows that Accellera was already moving up). 

To some extent these are two different worlds (when discussing verification recently with someone, I mentioned TLM… and got looked at like I had grown a second head because the person lived in the concrete pre-mask verification world). But if the vision of abstract-architecture-refined-to-finished-chip is to be realized, it can help to do that within a single body.

Minor details – like what the combined entity will be called – have yet to be worked out. The end of the year is pegged as the target for all such niceties.

This largely leaves Si2 as the other pre-IEEE standards body. Having two such entities ensures that it will still be possible to take two competing proposals from two competing companies and create two different standards through two different bodies*, both of them legit.

That’s SOP.

More in their release

 

*Scroll to the last section…

Leave a Reply

featured blogs
Sep 23, 2022
When I rejoined Cadence in 2015, we had not yet announced Palladium Z1. But it was basically done, and we announced it a couple of months later. I wrote about the announcement in my post Palladium Z1, an Enterprise Server Farm in a Rack . Next, we created Protium X1 which I c...
Sep 22, 2022
On Monday 26 September 2022, Earth and Jupiter will be only 365 million miles apart, which is around half of their worst-case separation....
Sep 22, 2022
Learn how to design safe and stylish interior and exterior automotive lighting systems with a look at important lighting categories and lighting design tools. The post How to Design Safe, Appealing, Functional Automotive Lighting Systems appeared first on From Silicon To Sof...

featured video

PCIe Gen5 x16 Running on the Achronix VectorPath Accelerator Card

Sponsored by Achronix

In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t FPGA is one of the first FPGAs that can natively support this interface within its PCIe subsystem. Speedster7t FPGAs offer a revolutionary new architecture that Achronix developed to address the highest performance data acceleration challenges.

Click here for more information about the VectorPath Accelerator Card

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Twinax Flyover Systems for Next Gen Speeds

Sponsored by Samtec

As the demand for higher and higher speed connectivity increases, we need to look at our interconnect solutions to help solve the design requirements inherent with these kinds of designs. In this episode of Chalk Talk, Amelia Dalton and Matthew Burns from Samtec discuss how Samtec’s Flyover technology is helping solve our high speed connectivity needs. They take closer look at how Samtec’s Flyover technology helps solve the issue with PCB reach, the details of FLYOVER® QSFP SYSTEM, and how this cost effective, high–performance and heat efficient can help you with the challenges of your 56 Gbps bandwidths and beyond design.

Click here for more information about Twinax Flyover® Systems for Next Gen Speeds