editor's blog
Subscribe Now

Your Standard Merger

Last week OSCI and Accellera decided to join forces. To some extent, this might be viewed as the union of the abstract and the concrete. OSCI lives in the world of SystemC and TLM; much of what Accellera does is further down the abstraction stack (although UVM shows that Accellera was already moving up). 

To some extent these are two different worlds (when discussing verification recently with someone, I mentioned TLM… and got looked at like I had grown a second head because the person lived in the concrete pre-mask verification world). But if the vision of abstract-architecture-refined-to-finished-chip is to be realized, it can help to do that within a single body.

Minor details – like what the combined entity will be called – have yet to be worked out. The end of the year is pegged as the target for all such niceties.

This largely leaves Si2 as the other pre-IEEE standards body. Having two such entities ensures that it will still be possible to take two competing proposals from two competing companies and create two different standards through two different bodies*, both of them legit.

That’s SOP.

More in their release

 

*Scroll to the last section…

Leave a Reply

featured blogs
Jun 2, 2023
Diversity, equity, and inclusion (DEI) are not just words but values that are exemplified through our culture at Cadence. In the DEI@Cadence blog series, you'll find a community where employees share their perspectives and experiences. By providing a glimpse of their personal...
Jun 2, 2023
I just heard something that really gave me pause for thought -- the fact that everyone experiences two forms of death (given a choice, I'd rather not experience even one)....
Jun 2, 2023
Explore the importance of big data analytics in the semiconductor manufacturing process, as chip designers pull insights from throughout the silicon lifecycle. The post Demanding Chip Complexity and Manufacturing Requirements Call for Data Analytics appeared first on New Hor...

featured video

Automatically Generate, Budget and Optimize UPF with Synopsys Verdi UPF Architect

Sponsored by Synopsys

Learn to translate a high-level power intent from CSV to a consumable UPF across a typical ASIC design flow using Verdi UPF Architect. Power Architect can focus on the efficiency of the Power Intent instead of worrying about Syntax & UPF Semantics.

Learn more about Synopsys’ Energy-Efficient SoCs Solutions

featured paper

EC Solver Tech Brief

Sponsored by Cadence Design Systems

The Cadence® Celsius™ EC Solver supports electronics system designers in managing the most challenging thermal/electronic cooling problems quickly and accurately. By utilizing a powerful computational engine and meshing technology, designers can model and analyze the fluid flow and heat transfer of even the most complex electronic system and ensure the electronic cooling system is reliable.

Click to read more

featured chalk talk

ADI's ISOverse
In order to move forward with innovations on the intelligent edge, we need to take a close look at isolation and how it can help foster the adoption of high voltage charging solutions and reliable and robust high speed communication. In this episode of Chalk Talk, Amelia Dalton is joined by Allison Lemus, Maurizio Granato, and Karthi Gopalan from Analog Devices and they examine benefits that isolation brings to intelligent edge applications including smart building control, the enablement of Industry 4.0, and more. They also examine how Analog Devices iCoupler® digital isolation technology can encourage innovation big and small!  
Mar 14, 2023
10,484 views