editor's blog
Subscribe Now

Scenarios – Certain and Less So

Feeling somehow less worthy in the shadow of the passing of Bob Pease… (with no offense intended towards Docea…)

I spent a few minutes with Docea at DAC a couple weeks ago. You may recall their Aceplorer product dealing with both power and thermal analysis. Two things caught my eye, one of which is a new feature, the other something they’re working on.

The new feature is scenario generation. This is particularly applicable to multi-mode designs, where different modes are exercised as different scenarios. Marketing might refer to them as high-level use cases. Not only is this intended for what-if analysis and architecture optimization, but the results can also be fed to virtual platforms for downstream evaluation.

The thing they’re working on is 3D IC modeling (who isnt’?). This is actually something they announced last year in association with French research group CEA-Leti. I learned a bit more about what it is they’re paying particular attention to.

While they can see their way clear on power modeling for 3D ICs, they’re tinkering a bit more with the thermal side to see if their approach can work. They don’t use a full solver for thermal analysis; they use thermal RC network models, and extending that to stacked dice and all of the bits and bobs that may end up in the sandwich for thermal or redistribution purposes makes it something less than a chip shot.

More info on their latest announcement (plus now-expired discussion of their DAC demos) in their release

Leave a Reply

featured blogs
Jul 3, 2020
[From the last episode: We looked at CNNs for vision as well as other neural networks for other applications.] We'€™re going to take a quick detour into math today. For those of you that have done advanced math, this may be a review, or it might even seem to be talking down...
Jul 2, 2020
Using the bitwise operators in general, and employing them to perform masking operations in particular, can be extremely efficacious....
Jul 2, 2020
In June, we continued to upgrade several key pieces of content across the website, including more interactive product explorers on several pages and a homepage refresh. We also made a significant update to our product pages which allows logged-in users to see customer-specifi...

featured video

Product Update: What’s Hot in DesignWare® IP for PCIe® 5.0

Sponsored by Synopsys

Get the latest update on Synopsys' DesignWare Controller and PHY IP for PCIe 5.0 and how the low-latency, compact, power-efficient, and silicon-proven solution can enable your SoCs while reducing risk.

Click here for more information about DesignWare IP Solutions for PCI Express

Featured Paper

Cryptography: Fundamentals on the Modern Approach

Sponsored by Maxim Integrated

Learn about the fundamental concepts behind modern cryptography, including how symmetric and asymmetric keys work to achieve confidentiality, identification and authentication, integrity, and non-repudiation.

Click here to download the whitepaper

Featured Chalk Talk

Hello FPGA

Sponsored by Mouser Electronics and Microchip

Getting started on an FPGA-based embedded vision project can be tricky. Locating all the components you need, getting them to talk to each other, and just getting your system to the video equivalent of “Hello World” is a pretty daunting task. In this episode of Chalk Talk, Amelia Dalton chats with Avery Williams of Microchip Technology about the Hello FPGA kit - a low-cost, low-touch embedded vision kit for engineers new to FPGAs.

More information about Microchip Technology Hello FPGA Kit