editor's blog
Subscribe Now

Greater Certitude

About two years ago, we looked at a new product from SpringSoft, Certitude, inherited through the acquisition of Certess. SpringSoft has just announced some improvements to the product.

As a quick reminder, Certitude performs what SpringSoft calls “functional qualification.” That fundamentally means that it looks for untestable pieces of your design by inserting bugs and seeing if the bugs can be detected.

Most of the improvements have to do with improving the specificity and relevance of what the analysis returns. First, they’ve tuned some of the kinds of errors they inject to align with the typical kinds of faults that might be found in an SoC. Second, they correlate results in a manner that eliminates a multitude of “hits” that might all relate to the same issue. This reduces the amount of “noise” in the results, making it easier to sift through. Third, results are ranked based on likely impact so that the most important issues can be addressed first.

They’re also introducing a new use mode intended for checking out the testbench setup. The focus of this is to prove out the checkers early on while the tests are still being written.

More info in their press release

Leave a Reply

featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Elevate Your Chip Design and Development with Synopsys.ai

Sponsored by Synopsys

Award-winning Synopsys.ai, the industry’s first full stack, AI-driven electronic design automation suite, offers AI-driven workflow optimization & data analytics solutions along with breakthrough generative AI capabilities for next-level chip design.

Click to read more

featured chalk talk

Nexperia Energy Harvesting Solutions
Sponsored by Mouser Electronics and Nexperia
Energy harvesting is a great way to ensure a sustainable future of electronics by eliminating batteries and e-waste. In this episode of Chalk Talk, Amelia Dalton and Rodrigo Mesquita from Nexperia explore the process of designing in energy harvesting and why Nexperia’s inductor-less PMICs are an energy harvesting game changer for wearable technology, sensor-based applications, and more!
May 9, 2023
26,394 views