This white paper summarizes performance as measured on the Spartan-6 FPGA Connectivity targeted reference design available with the Spartan-6 FPGA Connectivity Kit.
The results clearly demonstrate that:
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Throughput scales with variation in packet size.
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PCI Express performance improves with higher maximum payload size.
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CPU utilization improves with checksum offloading.
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An inverse relationship exists between packet size and CPU utilization.
The Spartan-6 FPGA Connectivity targeted reference design provides a high-quality, fully validated, and performance-profiled system that can help jump start end user development, thereby reducing time to market.
Author: Sunita Jain, Xilinx Corporation