industry news
Subscribe Now

Synopsys Launches New IP Subsystem to Accelerate Data Fusion Processing in IoT Devices

MOUNTAIN VIEW, Calif., Jan. 27, 2016 /PRNewswire/ —

Highlights:

  • Integrated, pre-verified IP subsystem includes the latest power-efficient DesignWare ARC EM9D and EM11D processors for highly-efficient DSP performance
  • Integrated microDMA controller provides 4X faster access times with lower system-level energy consumption by enabling data transfers during processor sleep modes
  • Tightly-coupled memory, peripherals and hardware accelerators reduce power consumption by up to 85 percent compared to discrete solutions
  • Software drivers and an extensive library of DSP functions such as FFT and DCT, FIR and IIR filters speed application software development
  • New IP offering extends Synopsys’ family of “Smart” subsystems optimized for IoT applications

Synopsys, Inc. (Nasdaq:SNPS) today announced the new DesignWare® Smart Data Fusion IP Subsystem, an integrated, pre-verified hardware and software IP product optimized for highly efficient DSP performance and ultra-low energy consumption. The Smart Data Fusion IP Subsystem offers a choice of DesignWare ARC® EM DSP processors, including the latest EM9D and EM11D cores with support for XY memory to boost signal processing performance. An integrated microDMA controller minimizes system-level energy consumption by enabling data transfers while the processor is in one of several programmable sleep modes. The integrated peripherals, memories, hardware accelerators and software DSP functions deliver the performance efficiency needed for common processing tasks in Internet-of-Things (IoT) applications such as always-on sensor fusion, voice and image detection and audio playback.

“IoT edge devices increasingly require a combination of low-power sensing capabilities and high-performance processing,” said Tadaaki Yamauchi, vice president of the Core Technology Business Division at Renesas Electronics Corporation. “Through our collaborative  demonstration platform, utilizing cutting-edge 40-nanometer embedded flash technology, Renesas and Synopsys show how designers can leverage complementary technologies such as Synopsys’ DesignWare Smart Data Fusion IP Subsystem with Renesas’ innovative, high-speed embedded flash memory controller IP to develop high-performance, cost-optimized IoT systems in less time.”

The DesignWare Smart Data Fusion IP Subsystem is designed to process data from numerous digital and analog sensors with minimal power consumption, offloading the host processor and enabling more efficient processing of sensor data. The fully configurable IP subsystem includes an ARC EM5D, EM7D, EM9D or EM11D processor. This family of power-efficient cores combines RISC and DSP processing and includes support for XY memory banks to enable a sustained throughput of one 32×32 MAC operation (or two 16×16 MAC operations) per clock cycle. The additional signal processing bandwidth is optimized to manage the extensive data processing required by advanced sensor fusion algorithms and to improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC. For example, executing codecs such as Bluetooth Low Complexity Subband Coding (SBC) with ARC processors requires less than 40 microwatts of power in 40-nanometer low-power processes with frequency (MHz) requirements more than 25 percent lower than competitive processor offerings.

The subsystem’s integrated microDMA controller enables memory and peripheral access during processor sleep modes and provides 4X faster access times compared to traditional bus-based DMA implementations. In addition, the subsystem incorporates highly-optimized I/O peripherals including multiple SPI, I2C and analog-to-digital converter interfaces, further lowering gate count and energy consumption while reducing engineering effort.

To ease software development, the subsystem includes software drivers and a rich library of off-the-shelf DSP functions supporting filtering, correlation, matrix/vector, decimation/interpolation and complex math operations. Designers can implement these sensor-specific DSP functions in hardware using a combination of native DSP processor instructions and tightly coupled hardware accelerators to boost performance efficiency and reduce power consumption. The subsystem is supported by commercially available software covering a range of IoT functionality, including speech recognition, voice control, motion sensing and audio post-processing and playback. Additionally, Synopsys’ embARC Open Software Platform gives software developers online access to a comprehensive suite of free and open-source software that accelerates code development for the subsystem.

“Advanced sensor fusion applications require a high level of integration with minimal power consumption and area,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “The new DesignWare Smart Data Fusion IP Subsystem gives designers a pre-verified hardware/software solution that delivers the additional DSP performance needed to manage specialized tasks like processing sensor information, recognizing voices and audio playback, while meeting the system’s power budget. By delivering a complete, pre-integrated IP subsystem, we enable designers to quickly incorporate this key functionality into their IoT devices with significantly less risk and effort.”

Availability

The DesignWare Smart Data Fusion IP Subsystem will be available in February 2016.

Learn more about the Smart Data Fusion IP Subsystem: https://www.synopsys.com/dw/ipdir.php?ds=smart-data-fusion-subsystem

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Exploring the Potential of 5G in Both Public and Private Networks – Advantech and Mouser
Sponsored by Mouser Electronics and Advantech
In this episode of Chalk Talk, Amelia Dalton and Andrew Chen from Advantech investigate how we can revolutionize connectivity with 5G in public and private networks. They explore the role that 5G plays in autonomous vehicles, smart traffic systems, and public safety infrastructure and the solutions that Advantech offers in this arena.
Apr 1, 2024
3,408 views