June 24, 2013

Going Local

Local Interconnect Is New. Or Not…

by Bryon Moyer

It snuck up and hit me during a Virtuoso presentation earlier this year by Cadence. It was a reference to “local interconnect.” It was the first such reference I had seen.*

For years I’ve been thinking in terms of silicon structures connected by metal through vias and contact holes. Does this mean that a completely separate set of interconnect was snaking around underneath the metal, where prying eyes (or at least my eyes) can’t see? (Don’t worry… the NSA knows it’s there…)

That wasn’t even half the insult. Here came the really humiliating part: when I started digging around, some folks from Cadence kindly (and without audibly rolling their eyes) forwarded me some older materials on local interconnect (LI). Like… from the 70s.

Ahem… OK… I remember the 70s… (during most of which, for the record, I was not an adult… I need to salvage some dignity from this situation!)

Granted, as I thought about it some more, I remembered that poly used to be used as a lower layer connecting close elements of transistors. “Close” being important, since it’s a high-resistivity material. But now I’m hearing that there are special rules for LI, and that it’s a new issue. That sounds like more than the innocuous little bits of poly that I (barely) remember.

Which raised the question for me: Is it the same? It can’t be completely the same, since there are new issues. So what’s changed?

Let’s start by going back and reviewing what LI is. Yes, for the most part, chips consist of devices buried in the substrate (OK, “buried” doesn’t work for FinFETS, but never mind…) and interconnected by layers of metal. The substrate stuff constitutes the “frontend of the line” and the standard metal interconnect and dielectrics are the “backend of line.” So the LI, which lies between the substrate and the metal, is sometimes called the “middle of the line” (MOL or MeOL… although I’m not sure the concept of a “middle end” works…).

If you think of this as being an extension of the use of poly, then you might think that the material is the biggest distinguishing feature from end-of-line metal. But, in fact, these days, LI involves metal. The real difference is that LI contacts silicon directly, without going through a contact hole. And multiple layers of LI overlap each other to make contact, and, again, they don’t use any intervening dielectric with vias.

The metals themselves form “silicides” where they contact the silicon directly. I intuitively think of this as a “softening” of the interface, with silicon diffusing up and metal diffusing slightly in to create the connections. There are variations called “salicides” and “polycides” that differ in the details of how they’re implemented.

The metals used can also vary, at least in theory. You’ll find references to copper, tungsten, titanium, and cobolt, although much of this reflects research, not necessarily what’s used in production.

Even though I came to this discussion through Cadence, it’s obviously not the tool guys that are driving this; they merely do what they’re told. (OK, with something like this that’s more than just a simple extension to what they were already doing, they probably push back a lot and ask, “Are you sure you’re really going to go into production with this?” And then do what they’re told.)

No, this obviously comes from the vaults of the process folks, dominated by IDMs and foundries. And the latter would be an obvious place to check on this, since what they do affects lots of you out there. So I contacted TSMC and GlobalFoundries.

TSMC’s response: “This is very specific to TSMC process technology so we will be unable to comment.”

Hoookay… GF was a bit more forthcoming. And here’s the deal as they explain it.

First, they noted that LI has been used for quite a while in memories. I did some Googling based on that and found an SRAM patent for SRAM cells with LI that was filed in 1999. And, well, it looked pretty broad: they claimed an SRAM that includes an “active structure” and a gate, with an insulator in between, and some kind of interconnect running between that gate and the active structure. (Yes, I’ve paraphrased. And, for any nervous lawyers, please don’t mistake this for inadvertent claims construction...)

It belongs to one Agere. Remember them? (If you really remember them, then your answer should be, “Which Agere?”) Actually, it belongs (or belonged) to Agere Systems Guardian Corp. So who knows where that is now. (Or whether it’s even still in force… I suppose it could have been challenged…)

Bottom line, they seemed to claim any SRAM that had one piece of LI in it, for whatever reason. But the relevant point is that LI is now coming to standard cells, and high-κ metal gates (HKMG) are a big part of the reason.

With HKMG, severe restrictions were placed on poly routing. That put a crunch on the local detailed routing that used to be done using poly within a cell (which means the old LI that was just poly), so this new scheme had to be introduced. Going with no LI is a problem because, if all you have is backend metal, dielectric, contact holes, and vias, then the design rules force a blowout in the cell size. Because the LI layers simply overlap, the cell can be kept nice and compact. Of course, if you want to connect the LI to the first layer of backend metal, that still happens through a via.

But apparently, doing this was not simple due to the need to manage a number of tradeoffs that GF cites:

                - Compatibility with HKMG

                - The need for independent active and poly contacts

                - High density routing without shorts

                - Optimizing lithography solutions

                - Keeping cost low

                - Allowing as many degrees of freedom as possible for routing

There’s no strict definition regarding the number of layers allowed, but, at least for GlobalFoundries, they’ve settled on two as being optimal. They say that the industry tried working with copper but ultimately moved to tungsten since it allowed them to use tighter spacing rules.

If, after this discussion, you’re thinking about LI as just another set of layers with the same flexibility as backend metal, then think again. According to Cadence, you can use only rectangles. Which kind of means that there is no real concept of “routing.” No jogs or bends are allowed. If you need to get from here to there along both x and y axes, then you need to be able to build a rectangle that gets you where you want to be.

And there are various other overlap rules as well that are said to be pretty complex. I guess hoping for anything simple out of anything new these days is a tad naïve…

If you’re wondering whether you’re going to have to monkey with LI anytime soon, that depends on what you do. If you’re involved with digital design, then LI will likely be used only by the folks building the standard cells, and you’re going to remain happily abstracted up in RTL-land. Custom and analog folks, on the other hand, still have to push their own polygons around, so this is really more relevant for them.

Which is why Cadence was talking about handling LI in Virtuoso. Which is how we got into this discussion in the first place.

 

*Well, that I can remember, anyway. Come to think of it, that’s a pretty important qualifier…

Channels

Analog/Mixed Signal. EDA. Semiconductor.

 
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Comments:


bmoyer

Total Posts: 407
Joined: Dec 2009

Posted on June 24, 2013 at 10:17 AM

How has "modern" local interconnect changed what you do, if at all?

primalchicken

Total Posts: 7
Joined: Apr 2012

Posted on June 25, 2013 at 1:39 PM

Excellent stuff again, Bryon.
The guys at LSI years ago used to refer to this as "metal zero." Some of the crew might have interesting perspectives on this, and I can refer you to a few.
I have to believe that IBM and Intel have very interesting perspectives as well.
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