November 14, 2011
Gate First vs. Last
A Summary of the Issue Now That Things Should Have Settled Down
There’s been a war out there, and it goes something like this:
“It can’t be done the old way anymore. We need to use the new way.”
“No, actually, we will be able to do it the old way.”
“No you can’t; it won’t be reliable.”
“Yeah, we can, and we already did, and it works.”
And what might this issue be? It’s something that ought to be so arcane as to be of no interest whatsoever to anyone who has a window in their surroundings – that is, anyone outside a fab. It’s a tussle over whether the gate of an MOS transistor should be built “first” or “last.”
But, for one company in particular, it’s taken a central role in their messaging: GLOBALFOUNDRIES is sticking with the old way of doing things for one more node.
Problem is, there’s not a lot of detail about the nature of the problem in all of the high-level messages. I’m sure folks got into infinite gory detail at the level of the work being done, but once it bubbled up through marketing and sales, well, not so much. Even poking around the internet didn’t yield much in the way of a plain-English discussion of the issues.
So I was left with the fundamental question, “Exactly what is at issue here?” And, beyond that, since it sounded like a simple “My way is better” argument, why would it be better only for one more node?
I got a chance to sit down with GLOBALFOUNDRIES’ Jim Ballingall to take an overall look at the issue. And I will attempt to summarize it here. Actually, it’s not that complicated, which is helpful.
MOS transistors have, for many generations, been built using a gate-first approach. What that means is that the gate is formed early, and it then acts as a mask for the source and drain implants. After implanting the source and drain, you need to anneal the wafer to repair the damage done during implantation (and establish the desired dopant profile).
We think of chips in simple terms as layers of silicon, oxide, poly, and metal. But there are often other little layers in there as well to help with lattice mismatches or adhesion or other physical properties that hold it all together. With a high-Κ metal gate, which is largely the game-changer, the stack consists of oxide, metal, and anything else they have to sandwich in there.
Here’s the problem: the anneal step can destroy the long-term integrity of that stack.
The solution to this is straightforward in principle: use a sacrificial gate to mask the implants, then remove it and build a new gate stack after the anneal step. In other words, the real gate is built last, after the source and drain have been formed.
Sounds easy, but it comes with a price. The gate metal has to be thinned down to the desired level using chemical/mechanical polishing (CMP). Think of it as a big pad with some kind of slurry grinding down the metal.
If you’ve done any buffing or grinding in your workshop – or heck, even just scrubbing something with a sponge – you may have noticed that soft spots go more quickly than hard ones, and your surface can end up irregular. This is particularly true for CMP – if there are wide areas without metal, then they tend to wear down faster, resulting in “dishing” or “cupping.” This is why metal fill is often used to fill up areas that are too sparse.
The potential for dishing has resulted in new “restrictive design rules” (RDRs) for the gate-last process. In particular:
- Poly can go in only one direction
- No wide capacitors are allowed
- Poly resistors get replaced by metal resistors, which have to be bigger due to their lower resistivity
The result is an overall density penalty of 10-20%.
So here’s the deal then: gate-last solves the gate stack issue, but it comes with an area penalty. If you can stick with gate-first, then you get a smaller circuit. The thing is, though, you can’t ignore the gate stack issue; you have to find another way around it.
And that’s where the “Can’t do it.” “Can too!” “Can not!” conversation arises.
GLOBALFOUNDRIES worked with IBM at their East Fishkill plant to find a different solution to the reliability of the gate stack. They won’t say what they did, but they refer to “materials integration” techniques, which involve subtle things like seed and cap layers that make the gate stack more than just metal over oxide.
And they claim that they’ve solved the issue and that they’ve tested it and burned it in and have reams of data proving that the results are reliable. That data is critical, given the counter-marketing suggesting that it won’t work. Hence their frequent message, which can be summed up as, “We did it, it works, and we’re open for business.”
So far, so good. But this is going to happen for only one process generation, 28 nm. Then they’re going to switch to gate-last at 20 nm. Just for comparison, Intel moved to gate-last at 45 nm, and TSMC went at 28 nm. So this whole kerfuffle is about a single node. Is GLOBALFOUNDRIES capitulating at 20 nm? What gives?
Not really. It turns out that, at 20 nm, a couple things conspire against further use of gate-first. A number of RDRs, like uni-directional poly, come into play at that node for other lithography-related reasons, so gate-first no longer helps with that. And these “materials integration” techniques apparently become harder at 20 nm.
So, basically, GLOBALFOUNDRIES has bought themselves one more node with gate first. Presumably they have fought so hard for this because it can give them a better area advantage against those competitors using gate-last. (And when you’re up against a behemoth like TSMC, any advantage can help.)
If GLOBALFOUNDRIES really has the data to back up their work, then the conflict should be over; they said they’d be able to do it, and they were right. But in any marketing war like this, you end up having to say it over and over and over again to counter the “they’ll never make it work” drumbeat from the other teams.
Posted on November 14, 2011 at 12:49 PMHave you ever had to prove you could do something someone else with a high profile said wasn't going to work well? Were you right?