June 29, 2010
Lattice Turns up the Tools
Diamond Re-vamps Design Experience
A fabless semiconductor company (as all FPGA companies are) is a curious entity. Since the company does not own its own production line, it doesn't really make anything. It has to differentiate itself and derive all of its value purely from intellectual property and services.
FPGA architectures are now well-known entities and are mostly beyond the reach of patent protection. Any company with the appropriate financial resources (and very little risk aversion) can draw up a new FPGA architecture, send it off to a company with a semiconductor fab, and start selling chips. (Don't try this at home, however. The world is littered with the corpses of failed startup companies attempted by some very savvy members of our industry.)
To compete, then, an FPGA company has to have an architecture (this is the easy part), enough money to get that architecture produced on a competitive process node (second easiest part), a sales and support organization that can make customers successful (this is where it gets really tricky), and a robust set of tools (which may well be the hardest thing).
Why are tools perhaps the hardest part? First, tools take both time and experience. To riff on the theme from the venerable "Mythical Man Month," an infinite number of software engineers could not produce a working set of FPGA tools in one year. (Or in five years.) In fact, without a significant number of users and a feedback loop to the developers, it is unlikely they would ever produce a successful working set of FPGA design tools.
To produce working FPGA design tools, one must first have a good set of non-working FPGA design tools and a large sample of designers willing to endure the frustration of discovering how and why those tools don't work. Then, over a long period of trial and error evolution, those tools can gradually become useful.
So, the best way to make excellent FPGA tools is to already have an FPGA company with real customers, existing tools, and a lot of experience.
Lattice Semiconductor fits that profile perfectly. The company has a long history in the FPGA business, a lot of experience with their legacy tools, and big motivation to create some differentiation against some very capable larger competitors.
Now, Lattice has taken the opportunity to do a complete re-vamp of their design tool suite. The new offering, dubbed "Diamond," focuses on improving the user experience and giving us the power to explore design alternatives easily with our FPGAs - one of the key reasons to choose an FPGA in the first place. The new suite builds upon years of customer experience with the current tool suite "ispLever," but it starts with a clean sheet on the user interface, design flow, and overall experience.
Diamond is oriented around giving a smooth flow through the FPGA design process with a consistent, intuitive user interface. It facilitates design exploration by organizing your design into alternative architectures (called "Implementations") and collections of tool options (called "Strategies"). So, if you have two different ideas for memory architectures in your design, you might code up your HDL both ways and save each version as a separate Implementation. The common code can be shared, and only the parts that differ in the two architectures can be unique. Then, you can try out each Implementation without having to fiddle around trying to manage and synchronize a "golden" copy of your design with various "experimental" copies.
In addition to variations of the design itself, you may want to have various pre-defined strategies for running the design tools. You can collect all the tool options for the implementation tools (synthesis, place-and-route, etc.) into a "Strategy" and apply various Strategies to your implementation. All of the Strategies can be saved, so you don't have to go back to try to re-create that perfect set of options that worked - back before you had that crazy idea late at night.
The overall user interface is modern and clean - with a tabbed, dockable/undockable model that makes it easy to keep track of where you are in your design and to keep the currently relevant information easily visible. There has been an emphasis on bringing the commonly used views up to the top level so you don't have to navigate down trees of menus and options repeatedly - particularly on tasks where you're iterating your design. Lattice has also taken the opportunity to standardize the operation of common functions across all the tools - eliminating some of the legacy confusion around different tools doing simple operations like zoom or select differently.
Third party synthesis tools are cleanly operated behind the curtain, driven by Diamond. You also have the option to use the native interfaces of those tools, of course - which comes in particularly handy if you're using advanced features in the UI of the full-priced versions. Diamond supports both Synopsys Synplify Pro and Mentor Precision. An OEM version of Synplify Pro is included.
Simulation is done via an export process and run in the simulator's native UI. This is a good thing, since putting a new skin on the simulators would be a huge effort with little payback. Aldec's simulator is included in an OEM version, but a variety of aftermarket HDL simulators are supported.
Also newly integrated into the environment is HDL Explorer - a neat set of capabilities Lattice acquired a few years back from a startup called Stelar Tools. HDL explorer gives a graphical view of your HDL hierarchy and allows sophisticated checking of HDL based on rule decks. Most people will find that the HDL checking will help them avoid most of the "duh" mistakes that cost time and frustration in repeated simulation/synthesis/place-and-route runs.
Diamond includes a "run manager" that can control and monitor the various steps of the design flow automatically. On a multi-core machine, it can also take advantage of the multi-processing capability to parallelize steps. The run manager cannot yet manage design tool execution across multiple machines on a network, but it's easy to see that as a future extension of the capability.
All of the source files, constraint files, scripts, reports, and other assorted objects associated with your design seem to be completely and cleanly managed by Diamond. Reports are easily accessible, and a variety of cross-probing options allow you to connect different views of your design. The reports panel allows you to see and compare both current reports and previous reports when you're iterating on your design.
Lattice has also added a lightweight ECO editor and a lite version of their programmer tool to support the fast-turnaround, iterative design exploration process, including quickly re-programming the device on your development board with an updated bitstream. For timing iteration, a new capability has been added that allows only timing analysis to be re-run (without re-running synthesis and/or place-and-route). This means that during timing debug, you can quickly try out constraint changes and see the impact without invoking the much longer implementation tool loop.
For your scripting adventures, Lattice has added complete TCL support, so just about anything you can do in the UI (and probably some things you can't) can be controlled via TCL - in batch or interactive mode. This is a major step up over the scripting support in their previous-generation tools.
Diamond is available now - as a free download or as a subscription. The subscription version is the same download as the free software, with the additional capabilities enabled by simple license upgrade. The free version includes support for Mach XO, XP, XP2, EC/P and ECP2 devices, and it includes Synplify Pro (Lattice Edition) plus Aldec Lattice Web Edition II simulator. The subscription license is available on an annual basis, and it adds support for SC/M, ECP2M and ECP3 devices, in addition to upgrading the simulator for mixed-language support and increased performance.
It's no secret that Lattice is not the leader in the FPGA market. However, they have some excellent, well-differentiated devices that are clearly a great choice for many applications. Updating the tool suite won't catapult them into a market leadership position, but it will bring a much higher degree of satisfaction to existing customers and will most likely put their products in consideration for many sockets where they might not have been competitive before. At first blush, Diamond looks to be a major upgrade to the design environment for Lattice's FPGAs that is bound to be well received by the company's faithful.