August 5, 2008
The Big eASY
eASIC Debuts 45nm FPGA Killer
What’s bigger, faster, cheaper, and lower-power than the biggest, newest 65nm and 40nm FPGAs?
ASICs, of course.
OK, I can hear you already –
“That’s not a fair comparison.”
“You need a team of 50 experts to design a high-end ASIC.”
“By the time you factor in NRE and mask costs, ASIC costs a lot more unless your volume is in the millions.”
“ASIC has very long design cycles.”
“ASIC is a high-risk game that only a small number of companies can afford.”
The list goes on and on. That’s why ASIC design starts have been on a steady decline for more than a decade.
What if there were an ASIC technology that didn’t have the usual drawbacks like high NRE, long design times, high risk, and complex tool flows?
This week, eASIC went a long way toward implementing that vision, announcing their new 45nm, “Nextreme-2,” “Zero Mask-Charge” ASIC family. eASIC has been around for awhile, and we’ve always been fascinated by their novel architecture. The devices use a logic cell structure that is analogous to the LUT fabric of an FPGA, but programming is accomplished by a “configurable via” that bridges between routing metal layers. Since this is a single mask layer, there is very little cost or risk involved in programming/customizing the devices. Furthermore, in early production, the via layer can be programmed via e-beam, allowing for very small (as in 1 unit) production runs. The company can easily produce a wafer with many designs from different companies, so there is no “minimum quantity” issue for setting up the fabrication process.
The benefits of the single-via metal customization go far beyond that, however. In an FPGA, all of the routing and look-up table (LUT) configuration is done via SRAM cells. This means that the majority of the transistors in a typical FPGA are involved with the configuration rather than the actual logic function. Any given design implemented in an FPGA will require many more active transistors (estimates are in the 5x-10x range) than that same design implemented in a metal-programmed technology. In today’s small process geometries (90nm, 65nm, and 45/40nm), oxides are so thin that these transistors leak – a lot. All those extra leaky transistors mean that your design will consume many times (5x-10x maybe?) more static power than its metal-programmed counterpart. Metal customization has benefits in speed and density as well, and those benefits are evident in eASIC’s new family.
The net result is a family of devices that ranges from 258K to a whopping 1.9 million eCells (an eCell is kinda’, sorta’ about the same as a LUT4). To get a rough comparison (albeit apples and oranges, or more like granny smith apples and crab apples) between this and Altera’s 40nm Stratix IV FPGAs (the only other 45/40nm devices that have been announced at this point) - Stratix IV tops out at about 680K logic elements plus a bunch of hard-wired IP. Therefore, eASIC’s Nextreme-2 is definitely higher-capacity than Stratix IV; we just can’t tell for sure how much. We’re not just picking on Stratix IV for sport, either. Stratix IV is by far the highest-density FPGA announced to date. 65nm and 90nm FPGAs currently offered by other vendors like Xilinx and Lattice Semiconductor don’t even come close.
Not surprisingly, eASIC is positioning Nextreme-2 directly against FPGAs. The rationale is sound. If you’re one of the well-heeled few that knows you need a cell-based ASIC and you have the resources and expertise to pull it off, you’re already on the ASIC channel (for the time being). Between that crowd and the high end of the FPGA rank, however, is a huge gap – a gap in unit cost, power consumption, speed, and actual logic density. If you need a custom device and can’t overcome the cell-based ASIC entry barriers, FPGAs have been your only reasonable alternative. You had to settle for the cost, power, and density compromises offered by those devices.
With Nextreme-2, eASIC is offering a wide span in that gap. Compared with FPGAs, the compromises are few – loss of in-system reprogrammability, 6-week device turnaround, and (possibly) slightly higher tool investment. The benefits are lower unit cost, lower power consumption, higher speed, and higher logic density. For many applications, this tradeoff will be attractive.
Perhaps the most direct comparison for Nextreme-2 would be with the cost-reduction offerings of Xilinx, Altera, and Lattice Semiconductor. All three companies offer a path to higher-volume cost reduction for FPGA designs. For Xilinx and Lattice, the cost reduction strategy amounts to buying FPGAs that were tested only for your specific design (therefore giving up reprogrammability) at a substantial discount (more than 50% unit cost savings – sometimes as high as 70-80%). Altera’s HardCopy is different. With HardCopy, you pay an NRE to get an ASIC fabricated that is a 1-1 match to the functionality and packaging of your FPGA design. (Again, of course, you’ve given up reprogrammability, but with HardCopy you’ve picked up better power consumption and potentially better performance.) Compared with all these strategies, Nextreme-2 has zero NRE, probably lower unit cost (based on early released data), similar turnaround time, and better performance, density, and power consumption.
By the numbers, Nextreme-2 (and its sibling, Nextreme-2T) comprise 8 family members. Nextreme-2 has 6 densities ranging from 258K eCells to 1.9M eCells, and Nextreme-2T has two densities – 1M eCells and 1.9M eCells (also boasting 48 and 56 6.5 Gbps Multi-Gigabit transceivers respectively). On-chip memory ranges from 4Mb to about 30Mb, and user I/O ranges from 464 to 1288. I/O support includes PCIe Gen 2.0, Interlaken, Double XAUI, SATA, SRIO, CPRI, OBSAI, HD/SDI, SFI-5, Fibre-channel, and many others.
The design flow for Nextreme-2 is remarkably similar to that of an FPGA. eASIC provides a suite of tools that assist with I/O design, memory design, and a host of other system-level issues. Physical Synthesis (including placement) is accomplished with Magma’s BlastCreate SA. Placement, routing and subsequent configuration are accomplished with proprietary tools from eASIC. Design handoff can be either at the RTL level or, for those of you that like the maximum control, after place-and-route. A formal verification flow is also available for those of you that don’t like to stay up nights worrying if your devices will come back working after six weeks.
In the IP space, many will question the absence of the usual FPGA-style DSP blocks and hard-wired multipliers. The answer to this is simple and intuitive. Since the logic fabric itself is hard-wired, there is almost no penalty to implementing multipliers in the fabric compared with hand-optimized hard blocks. The advantages to this approach are that you create only the number of multipliers you need, and you can create exactly the size and shape of multiplier your design requires rather than trying to shoehorn everything into 18X18 pre-fab units. If your design has some bizarre requirement for 7X22 multiplication – no problem, just build one.
Along with multipliers, most of today’s large system-on-chip designs involve a processor core. The story here is decidedly ASIC-like. Since the fabric performs a lot more like a traditional ASIC, the ASIC-grade versions of popular processors from companies like ARM and Tensilica can be used. If you have a pre-existing investment in software IP for a particular processor core, you can probably roll right into a Nextreme-2 device with little effort.
eASIC has obviously thought a lot about the power problem as well. Support is included for a variety of clock gating strategies, and a “standby” mode is also available for putting the device (or parts of it) to sleep. Additionally, all of the unused logic is automatically disabled so those transistors aren’t passively leaking while the rest of your design is running.
Based on the track record of eASIC’s 90nm offering (they are claiming over 120 design wins in 18 months), we’d expect a lot of traction for this new family. The company claims an application domain similar to that of high-end FPGAs, but with a decidedly higher-volume bent. This could spell bad news for FPGA companies in their traditional stronghold application areas like network switches, as eASIC’s parameters are a good fit for many parts of that market.
eASIC says that lead customers have designs underway now with tape-outs scheduled for Q3 this year (Hey, isn’t that this quarter?) and that general release of Nextreme-2 will be in Q4 of this year with the SerDes-transceiver- equipped Nextreme-2T scheduled for Q2, 2009.