Achieving timing closure in today’s increasingly large and complex digital integrated circuit designs – irrespective of whether they are realized using FPGA, Structured ASIC, or even Standard Cell ASIC fabric – is becoming evermore problematic with the latest design targets running at aggressive clock speeds. The majority of today’s designers typically code in RTL using … Read More → "Are You Designing with Too Many Significant Figures?"

Extracting higher performance from today’s FPGA-based systems involves much more than just cranking up the clock rate. Typically, one must achieve a delicate balance between a complex set of performance requirements – I/O bandwidth, fabric logic, memory bandwidth, DSP and/or embedded processing performance – and critical constraints such as power restrictions, signal integrity and cost … Read More → "Need More Performance?"

As FPGAs grow faster and more powerful, our natural inclination is to scrape more and more functionality off our boards and cram it into our new, bigger FPGAs. It’s a strategy that makes good sense. Not only do we save board real estate, increase reliability, and cut bill of materials (BOM) cost, but we also … Read More → "Looking Inside"

If March winds bring April showers, then April showers must somehow give rise to new announcements in programmable logic and structured ASIC. From tools to technology to applications, let’s sail through some of the most interesting announcements this week to pick up on the latest trends. There continue to be significant advances in the design … Read More → "Mayday Mayhem"

Tom Hart took physics in school and was a Bombardier-Navigator in the U.S. Navy. He knows that with proper focus you can take advantage of an exponential ratio to deliver many times more energy to a target than even a much larger unfocused source. As Chairman, President, and CEO of QuickLogic, he applies that same … Read More → "E. Thomas Hart"

I still check occasionally on gizmodo.com or engadget.com, but I’ve pretty much given up hope. It’s now 2005. Throughout my childhood, I was convinced that by this year I’d be flying around in my jetpack, or at least driving my flying car. My personal robot is a bit closer to reality, but still not in … Read More → "Leading Languages"

Your design is working perfectly – on your development board. Unfortunately, your company is probably not planning to ship FPGA development boards as part of their product. You’ll have to come up with something a little more practical and cost effective if you’re going to win “employee of the decade” when your skunk-works design ships … Read More → "Cost-Reduction Quagmire"

In our previous article “Terminology Tango 101” we poked fun at the myriad metrics given by programmable logic companies in their publications and data sheets. While it’s fun to make fun of the confusion induced by this dizzying data, it is also interesting and useful to dig past the difficulties of agreeing on units and … Read More → "Benchmarking Battlefield"