Northwich, Cheshire, 2^nd September 2010. Kane Computing Ltd (KCL), today announced that the popular Impulse C to FPGA tool set, that they sell in the UK has now been integrated to Stone Ridge Technology products. The integration enables software developers to write HLL (High Level Language) signal, imaging or data processing algorithms that rapidly compile to optimized … Read More → "C-to-FPGA Integration Accelerates DSP Prototyping by ten"

MOUNTAIN VIEW, Calif. – September 07, 2010 – CEVA, Inc. [(NASDAQ: CEVA); (LSE: CVA)], the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the CEVA-X1643™, a  highly-energy efficient,1 GHz DSP core designed to boost overall chip performance for a broad range of applications including wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is the latest family member of the widely used CEVA-X DSP architecture, which has been licensed by more than 25 customers and shipped in over 100 million devices to … Read More → "CEVA’s New 1 GHz Programmable DSP Core Offers Exceptional Performance and Power Efficiency for Next Generation Communications and Multimedia SoCs"

Oslo, Norway, September 2, 2010 – Energy Micro®, the energy efficient microcontroller company, has introduced a free software tool designed to remove the traditionally time-consuming problem of debugging I/O pin conflicts.  Supporting the complete EFM32 Gecko low power MCU family, energyAware Designer ensures correct pin configuration and automatically generates set-up code and documentation.

On creating a new project, designers select a target MCU and are presented with a default device configuration.  Clicking on a peripheral function enables it and highlights respective pins in green on an intuitive pin-out diagram.  Pin-conflicts induced by selecting another peripheral, … Read More → "Energy Micro tool instantly resolves MCU pin conflicts"

Starnberg, August 31, 2010 – qaqadu event gmbh, expert for technical education, again offers technical short courses on engineering topics starting in October 2010. Thus meeting the further increasing demand for information on topics such as digital signal processing and FPGAs (Field Programmable Gate Arrays), qaqadu will present the following courses: FPGAs for embedded processors (October 12-14, 2010). DSP for FPGAs (November 16-19, 2010), and DSP Theory, Algorithms and Architectures (December 7-10, 2010). The courses are going to take place in Munich, Germany. The instruction language is English.

Special attention is paid to practical experience; after each presentation a hands-on session will follow in … Read More → "Technical Education on Digital Signal Processing, FPGAs and Embedded Processors"

About IO Checker 

IO Checker will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins.

Read More → "HDL Works Presents ‘IO Checker 2.0’"

Shanghai, China – Aug 27^th, 2010 – SoCIP 2010 Road Show seminars will be making stops at Shenzhen on Sep 7^thRead More → "SoCIP Road Shows to Stop at Shenzhen, Chengdu and Xi’an"

San Jose, Calif. – August 30, 2010 – S2C Inc., a rapid SoC prototyping provider, announces the release of its fourth-generation rapid SoC prototyping tool, V6 TAI Logic Module, based on Xilinx’s 40-nm Virtex™ field-programmable-gate-array (FPGA).  

Each … Read More → "S2C Announces Virtex-6 Based 4th Generation Rapid SoC Prototyping Solution"

WILSONVILLE, Ore., August 26, 2010—Mentor Graphics Corporation (NASDAQ: MENT) today announced it has collaborated with GLOBALFOUNDRIES to create a facility called Graphical Design Rule Manual (GDRM) that helps IC designers rapidly debug layout design rule violations by integrating the Calibre® RVE™ results viewing environment with GLOBALFOUNDRIES’ electronic design rule manuals. With GDRM, designers using the Calibre RVE tool to correct DRC hotspots can automatically access detailed GLOBALFOUNDRIES textual and graphical reference information about the specific rules generating the violations. By providing instant access to relevant information, the solution allows designers to fix errors more quickly and … Read More → "Mentor Graphics Collaborates with GLOBALFOUNDRIES to Provide Easier Debugging Capability to IC Designers"

MOUNTAIN VIEW, Calif., Aug. 25 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Global Unichip Corporation (GUC) has achieved first-pass silicon success for its GP5080 Solid State Drive (SSD) system-on-chip (SoC) utilizing the complete Synopsys DesignWare® SATA IP solution, consisting of controller, PHY and verification IP. GUC, a leading full-service SoC design foundry, determined that Synopsys’ DesignWare SATA IP was superior in quality, power consumption, performance and feature … Read More → "Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation"

MOUNTAIN VIEW, Calif., Aug. 24 /PRNewswire-FirstCall/ — Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced immediate availability of the DesignWare® MIPI M-PHY® IP for next-generation high-speed interfaces based on the newly ratified MIPI® Alliance M-PHY specification. With this latest addition to the DesignWare MIPI IP portfolio, Synopsys is the first provider to offer a comprehensive solution of a controller and PHY IP for both the MIPI DigRF(SM) v3 (2.5 … Read More → "Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology"