News – Page 2245 – EEJournal

ChipEstimate.com Launches First Third-Party IP Portal Localized for Vital Japanese Design Community

May 19, 2011

ChipEstimate.com, a Japanese-language version of the world’s largest IP and chip planning portal. ChipEstimate.jp allows Japanese IC designers to evaluate and explore third-party IP in their native language, providing access to a global ecosystem of IP from over 200 of the world’s largest IP suppliers and foundries. The site also makes it easier for Japanese IP suppliers to join, potentially expanding an already extensive database of over 8,000 pieces of IP and, in turn, giving those suppliers access to the over 30,000 users in the global ChipEstimate.com community. Spending … Read More → "ChipEstimate.com Launches First Third-Party IP Portal Localized for Vital Japanese Design Community"

TriQuint Semiconductor, Agilent Technologies Collaborate on Next-Generation Wireless Design Flow

May 19, 2011

HILLSBORO, Ore., and SANTA CLARA, Calif., May 18, 2011 – TriQuint Semiconductor (NASDAQ: TQNT) and Agilent Technologies Inc. (NYSE: A) today announced results for building next-generation RF solutions. This includes enhanced TriQuint process design kits with support for Agilent’s Advanced Design System 2011 EDA software and the development of an ADS RF Module PDK for TriQuint’s RFIC/MMIC and RF Module integrated design flow.

The upgraded ADS Foundry PDKs enable both TriQuint’s foundry customers and in-house design engineers to take advantage of new capabilities in ADS 2011. Specifically, the PDKs provide a fully integrated … Read More → "TriQuint Semiconductor, Agilent Technologies Collaborate on Next-Generation Wireless Design Flow"

Researchers Develop Hardware Encryption For New Computer Memory Technology

May 18, 2011

Security concerns are one of the key obstacles to the adoption of new non-volatile main memory (NVMM) technology in next-generation computers, which would improve computer start times and boost memory capacity. But now researchers from North Carolina State University have developed new encryption hardware for use with NVMM to protect personal information and other data.

NVMM technologies, such as phase-change memory, hold great promise to replace conventional dynamic random access memory (DRAM) in the main memory of computers. NVMM would allow computers to start instantly, and can fit more memory into the same amount of space used … Read More → "Researchers Develop Hardware Encryption For New Computer Memory Technology"

EVE Integrates ZeBu with ARM VSTREAM Virtual Debug Interface

May 18, 2011

SAN JOSE, CALIF. –– May 18, 2011 –– EVE, the leader in hardware/software co-verification, announced today it has integrated its best-in-class ZeBu hardware-assisted verification solution with the fast and flexible ARM® VSTREAM™ Virtual Debug Interface.

The integration of the VSTREAM transactor with the EVE ZEMI-3 transactor compiler that now links ZeBu emulated system-on-chip (SoC) designs with a variety of software debuggers improves embedded software debug for ARM processor-based devices. This integration eliminates the need for … Read More → "EVE Integrates ZeBu with ARM VSTREAM Virtual Debug Interface"

Vennsa Unveils OnPoint with Powerful Triage Engine, Enhanced Accuracy, Increased Capacity

May 18, 2011

TORONTO –– May 18, 2011–– Vennsa Technologies Inc., the leading supplier of automated functional verification debugging and error localization software, today announced immediate availability of OnPoint™ with Triage, along with a set of performance-driven features to enhance accuracy and increase capacity.

“Manual error localization and debugging consume more than 60% of the verification effort,” remarks Andreas Veneris, president and chief executive officer of Vennsa Technologies. “The verification community strongly advocates … Read More → "Vennsa Unveils OnPoint with Powerful Triage Engine, Enhanced Accuracy, Increased Capacity"

Nominations for EDA Industry’s Annual Phil Kaufman Award Open Through June 30

May 18, 2011

SAN JOSE, Calif. and NEW YORK — May 18, 2011 — Nominations are being accepted now through Thursday, June 30, for the Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation (EDA) sponsored by the EDA Consortium (EDAC) and the IEEE Council on Electronic Design Automation (CEDA).

Last year’s recipient was Pasquale (Pat) O. Pistilli, chairman of MP Associates of Louisville, Colo., who pioneered the EDA industry and built the Design Automation Conference as its premiere showcase and networking platform.

The award, to be presented at a dinner ceremony in October in … Read More → "Nominations for EDA Industry’s Annual Phil Kaufman Award Open Through June 30"

EVE Expands ZeBu Line with New Vertical Solutions

May 18, 2011

SAN JOSE, CALIF. –– May 18, 2011 –– EVE, the leader in hardware/software co-verification, today began shipping four new vertical solutions, further expanding its best-in-class ZeBu hardware-assisted verification family into computer/peripherals, embedded processors, networking and video markets.

The addition of PCI-Express 3.0, Multiport Gigabit Ethernet, USB and HDMI transactors underscores EVE’s commitment to grow its catalog of verification intellectual property (VIP) components to support system-on-chip (SoC) verification in a broad range of markets.

ARM Upgrades Validation Methodology for Processor and System IP With Jasper

May 18, 2011

MOUNTAIN VIEW, CA–(Marketwire – May 18, 2011) – Jasper Design Automation, the leading provider of verification solutions based on formal technology, today announced that ARM has completed a deployment of Jasper technology and solutions that enhances the validation methodology for ARM^® AMBA^® protocol-based processor and system IP. The adoption enables design and validation teams at ARM to address a wide range of verification issues such as the absence of deadlocks, cache coherency, x-propagation detection, control register verification, and protocol certification.

“We selected Jasper’s formal verification technology to be deployed across our … Read More → "ARM Upgrades Validation Methodology for Processor and System IP With Jasper"

NXP Showcases Base Station TRx Component Demonstrator for LTE / LTE Advanced Wireless Air Interface Standards at IMS 2011

May 18, 2011

EINDHOVEN, NETHERLANDS–(Marketwire – May 18, 2011) – NXP Semiconductors N.V. (NASDAQ: NXPI) will demonstrate a component for a complete, mixed signal, Base Transceiver Station (BTS) radio at the IEEE International Microwave Symposium (IMS 2011) to be held June 5-10 in Baltimore, Maryland (booth #420). The NXP BTS transceiver component demonstrator fully supports the demanding requirements of leading-edge wireless air interface standards, such as LTE Advanced, and showcases NXP’s … Read More → "NXP Showcases Base Station TRx Component Demonstrator for LTE / LTE Advanced Wireless Air Interface Standards at IMS 2011"

IAR Systems delivers complete starter kit for low-power STM32L family

May 18, 2011

Uppsala, Sweden—May 18, 2011—IAR Systems today announces a new kit for STMicroelectronics’ ARM Cortex-M3 based STM32L family with all necessary hardware and software for evaluation and prototyping included. IAR KickStart Kit for STM32L includes an evaluation board featuring an STM32L152VB microcontroller, LCD and other peripherals, an IAR J-Link Lite debug probe providing JTAG and SWD connections to the board, and a CD with software tools, example projects, and board support packages for different RTOSes.

The STM32L family is designed for low-power applications. When the board is connected to … Read More → "IAR Systems delivers complete starter kit for low-power STM32L family"

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