San Diego, CA  – Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, invites Design Automation Conference (DAC) attendees, to several Accellera and DAC events:

• On Sunday, DAC will hold a Universal Verification Methodology (UVM™) Workshop.
• On Tuesday, Accellera and its members, Cadence, Mentor and Synopsys, will host a UVM User … Read More → "Accellera Shares Electronic Design Standards Information at the Design Automation Conference; Events Focus on UVM, IP-XACT and IP Tagging"

San Diego, CA – May 19, 2011 – Real Intent Inc., the leading provider of software products that accelerate Advanced Sign-Off Verificationof electronic designs, today announced it will highlight its latest technology and proven solutions at this year’s 48^th Design Automation Conference (DAC) in San Diego, California, June 6-8, 2011. Real Intent will feature its Ascent™ XV solution, the industry’s first and only solution for comprehensive X-verification and sign-off. Ascent … Read More → "Real Intent Highlights Latest Technology for Advanced Sign-Off Verification at DAC 2011"

Campbell, CA, May 18, 2011 – Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company, in the post-layout verification market focused on solutions for nanometer design applications, announced today that it is introducing the industry’s first commercial hierarchical 3D extractor, H3D, for post-layout verification. H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity, and field-solver accuracy. H3D works with design flows from the leading EDA suppliers.

“Post-layout verification is a major bottleneck in today’s leading edge designs,” … Read More → "Silicon Frontline Announces First Commercial 3D Hierarchical Extractor"